Memory Map
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
3-5
Y: $FF_FFC3–$FF_FFC0
WDT
WDT_1
Y: $FF_FFBF–$FF_FFB0
Reserved
Reserved
Y: $FF_FFAF–$FF_FFA0
Reserved
Reserved
Y:$FF_FF9F–$FF_FF80
ESAI_1
ESAI_3
Y:$FF_FF7F–$FF_FC40
Reserved
Y:$FF_FC3F–$FF_FC00
ASRC
Y:$FF_FBFF–$FF_E000
Reserved
Table 3-7. Detailed Device X-Memory Map
Peripherals
Address
Register Name
1
PIC, PIC_1
X: $FF_FFFF
Interrupt Priority Register Core (IPR-C)
X: $FF_FFFE
Interrupt Priority Register Peripheral (IPR-P)
X: $FF_FFFD
Reserved
CIM, CIM_1
X: $FF_FFFC
OnCE Global Data Register (OGDB)
PIC, PIC_1
X: $FF_FFFB
Interrupt Priority Register Core (IPR_C1)
X: $FF_FFFA
Interrupt Priority Register Peripheral (IPR_P1)
X: $FF_FFF9
Reserved
CIM, CIM_1
X: $FF_FFF8
DMA stall register (DMAS).
X: $FF_FFF6
Reserved
X: $FF_FFF5
CHIP ID Register (CHIDR)
DMA, DMA_1
X: $FF_FFF4
DMA Status Register (DSTR)
X: $FF_FFF3
DMA Offset Register 0 (DOR0)
X: $FF_FFF2
DMA Offset Register 1 (DOR1)
X: $FF_FFF1
DMA Offset Register 2 (DOR2)
X: $FF_FFF0
DMA Offset Register 3 (DOR3)
DMA, DMA_1
Channel 0
X: $FF_FFEF
DMA Source Address Register (DSR0)
X: $FF_FFEE
DMA Destination Address Register (DDR0)
X: $FF_FFED
DMA Counter (DCO0)
X: $FF_FFEC
DMA Control Register (DCR0)
Table 3-6. Y-Memory Map for DSP Core-0 and Core-1 (Continued)
Address Range
Blocks
DSP Core-0
DSP Core-1