Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
18-24
Freescale Semiconductor
S/PDIF—Sony/Philips Digital Interface
On receiving an Underrun or Overrun interrupt, the synchronization between Left and Right
words in the FIFOs may be lost. Synchronization will not be lost when the Underrun or
Overrun comes from the IEC958 side of the FIFO. If the processor reads or writes more data
from the left than from the right (for example), synchronization will be lost. If automatic
resynchronization is enabled, and if the software obeys the rules to let this work,
resynchronization will be automatic.
18.4.2
Channel Status Transmission
A total of 48 Consumer channel status bits are transmitted from two registers. Channel Status Bits are
ordered first bit left. CS-channel MSB bit “0” is located in bit position 23 in the memory-mapped register
SPDIFTxCChannelCons_h. CS-channel bit “23” is considered bit 0 in the register. C-channel bits 24–47
are seen as MSB–LSB bits of register SPDIFTxCChannelCons_l.
A total of 32 Professional channel status bits are transmitted from one register. Channel Status Bits are
ordered first bit left. CS-channel MSB bit “0” is located in bit position 7 in the memory-mapped register
SPDIFTxCChannelProf_h. CS-channel bit “7” is considered bit 0 in the register. C-channel bits 8–31 are
seen as MSB–LSB bits of register SPDIFTxCChannelProf_l.
18.4.3
Validity Flag Transmission
The validity bit setting is selected using bit 5 of the SPDIFConfig register.