Clock Generation Module (CGM)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
7-9
20–16
R4–R0
Input Divider
Defines the input divider’s value that is applied to the input frequency. R[4:0] can be any value from
0–31. NR = R[4:0] + 1
Fout (pll) = (Fin * NF) / (NR*NO)
15–14
OD1–OD0
Output Divider
Defines the output divider value. The output divide factor divides the VCO output frequency by a factor
of 1, 2, 4 or 8:
OD1,OD0 = 2’b00: divide by 1 (NO = 1)
OD1,OD0 = 2’b01: divide by 2 (NO = 2)
OD1,OD0 = 2’b10: divide by 4 (NO = 4)
OD1,OD0 = 2’b11: divide by 8 (NO = 8)
Fout (pll) = (Fin * NF) / (NR*NO)
13
PEN
PLL Enable
Enables PLL operation. When PEN is set, the PLL is enabled and the internal clocks are derived from
the PLL VCO output. When PEN is cleared, the PLL is disabled and the internal clocks are derived
directly from the EXTAL signal.
When the PLL is disabled, the VCO stops to minimize power consumption. The PEN bit may be set or
cleared by software at any time during the device operation.
12
PSTP
PLL Stop State
Controls the PLL and on-chip crystal oscillator behavior during the Stop processing state. When PSTP
is set, the PLL remains operating while the chip is in the Stop state. When PSTP is cleared and the
device enters the Stop state, the PLL is disabled, to further reduce power consumption.
PSTP, PEN = 2’b0x: PLL disabled. (Only in system Stop mode.)
PSTP, PEN = 2’b10: PLL is enabled always but is in bypass mode.
PSTP, PEN = 2’b11: PLL is enabled always and is in non-bypass mode.
11
Reserved. Must be written “0” to preserve future compatibility.
10–8
DF2–DF0
Division Factor
Define the division factor (DF) of the low-power divider. These bits specify the DF as a power of two
in the range of 2
0
to 2
7
.Changing the value of the DF[2:0] bits does not cause a loss of lock condition.
Whenever possible, changes of the operating frequency of the device (for example, to enter a
low-power mode) should be made by changing the value of the DF[2:0] bits rather than by changing
the F[7:0] bits.
The operating frequency:
Fsys = Fout / (2
DF[2:0]
)
7–0
F7–F0
Multiplication Factor
Defines the multiplication factor (MF) that is applied to the PLL input frequency. The MF can be any
integer from 0 to 255. NF = F[7:0] +1.
Fout (pll) = (Fin * NF) / (NR*NO)
Table 7-8. PLL Control Registers Field Description (Continued)
Bit
Name
Description