Freescale Semiconductor Symphony DSP56724, Reference Manual

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Clock Generation Module (CGM)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor 7-5
Figure 7-2. Internal PLL Block Diagram
The PLL has a programmable output frequency (from 25 to 500 MHz), configured using a 5-bit input
divider, an 8-bit feedback divider and a 2-bit output divider. A 50% duty cycle for output clocks can be
achieved by enabling the output divider. The PLL can also be used as a clock buffer in a bypass mode,
which bypasses and powers down the PLL. A full power-down mode is also available.
7.2.4.1 PLL Operating Modes
There are three PLL operating modes: normal, bypass, and power-down.
• Normal Mode: The output clock frequency is programmable using the divider setting of R[4:0],
F[7:0] and OD[1:0]. When the divider settings are changed, the PLL must enter the power-down
mode (PD = HIGH) for more than 50 ns (a PD timing requirement, see
Table 7-3 ).
• Bypass Mode: The FIN is buffered directly to FOUT, bypassing the PLL, which is powered down.
A TRDY time (pull-in + lock time) is required for the PLL to lock when switching from Bypass
Mode to Normal Mode.
• Power-down Mode: The entire PLL cell is powered down internally, and FOUT is set to 1 V.
A TRDY time (pull-in + lock time) is required for the PLL to lock when switching from
Power-down Mode to Normal Mode.
Table 7-3. PLL Output Configurations
PD BP OD Description Fout
0 0
0
Normal Mode
F
REF
* NF
1 F
REF
* NF/2
2 F
REF
* NF/4
3 F
REF
* NF/8
0 1 x Bypass Mode F
IN
1 x x Power-Down Mode 1
Input
Divider
PDF
Charge
Pump
Loop
Detector
Loop
Filter
Feedback
Divider
Output
Divider
Buffer
F
IN
R[4:0]
F[7:0]
PD
OD
BP
F
OUT
LD
Mux
F
ref
F
bck
VCO