Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-90
Freescale Semiconductor
External Memory Controller (EMC)
For data timings only the propagation delay of one buffer plus the actual data set-up time has to be
considered.
Figure 21-53. GPCM Data Timing
21.5.2
Bus Turnaround
Because the EMC uses multiplexed address and data, give special consideration to avoid bus contention
at bus turnaround. The following cases must be examined:
•
Address phase after previous read
•
Read data phase after address phase
•
UPM cycles with additional address phases
Because the bus does not change direction, the following cases do not require special attention:
•
Continued burst after the first beat
•
Write data phase after address phase
•
Address phase after previous write
21.5.2.1
Address Phase after Previous Read
During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives LAD. After the
data has been sampled, the output drivers of the external device must be disabled. This can take some time;
for slow devices the EHTR feature of the GPCM or the programmability of the UPM should be used to
guarantee that those devices have stopped driving the bus when the EMC memory controller ends the bus
cycle.
In this case, after the previous cycle ends, LBCTL goes high and changes the direction of the bus
transceiver. The EMC then inserts a bus turnaround cycle to avoid contention. The external device has now
already placed its data signals in high impedance and no bus contention will occur.
21.5.2.2
Read Data Phase after Address Phase
During the address phase, LAD actively drives the address and LBCTL is high, driving bus transceivers
in the same direction as during a write. After the end of the address phase, LBCTL goes low and turns
around the direction of the bus transceiver. The EMC places the LAD signals in high impedance after its
t
dis
(LB). The LBCTL will have its new state after t
en
(LB), and because this is an asynchronous input, the
transceiver starts to drive those signals after its t
en
(transceiver) time. To avoid bus contention, you have to
ensure that [t
en
(LB) + t
en
(transceiver)] is larger than t
dis
(LB).
LAD[23:0]
LBCTL
Buffer
Device
input
D
pin
Muxed
Address and
Data
Buffered
Data
EMC
