Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
5-10
Freescale Semiconductor
Core Configuration
Figure 5-1. Core-0 Interrupt Priority Register P
Figure 5-2. Core-0 Interrupt Priority Register C
Figure 5-3. Core-0 Interrupt Priority Register C1
ESL0
ESL1
SHL0
SHL1
23
22
21
20
19
18
17
16
15
14
13
12
0
1
2
3
4
5
6
7
8
9
10
11
ESAI IPL
SHI IPL
Reserved
Reserved
ESAI_1 IPL
ESL11
TAL0
TAL1
EMC/ICC Error IPL
TRIPLE TIMER IPL
ESL10
SPDIF Rx IPL
SPRL0
SPRL1
SPTL0
SPTL1
ICIL0
ICIL1
ICAL0
ICAL1
ASL0
ASL1
SPDIF Tx IPL
ASRC Rx IPL
ICC INT IPL
ICC ACK INT IPL
LIEL0
LIEL1
IAL0
IAL1
IAL2
IBL0
IBL1
IBL2
ICL0
ICL1
ICL2
0
1
2
3
4
5
6
7
8
9
10
11
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
D0L0
D0L1
D1L0
D1L1
23
22
21
20
19
18
17
16
15
14
13
12
DMA ch0 IPL
DMA ch1 IPL
D2L0
D2L1
D3L0
D3L1
D4L0
D4L1
D5L0
D5L1
DMA ch2 IPL
DMA ch3 IPL
DMA ch4 IPL
DMA ch5 IPL
IDL2
IDL1
IDL0
IRQD mode
D6L0
D6L1
D7L0
D7L1
0
1
2
3
4
5
6
7
8
9
10
11
DMA ch6 IPL
DMA ch7 IPL
13
12
14
15
16
17
18
19
20
21
22
23
Reserved
Reserved