Memory Map
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
3-15
ESAI_1,ESAI_3
Y:$FFFF9F
Port E/E1 Control Register (PCRE)
Y:$FFFF9E
Port E/E1 Direction Register (PPRE)
Y:$FFFF9D
Port E/E1 GPIO Data Register (PDRE)
Y:$FFFF9C
ESAI_1/3 Receive Slot Mask Register B (RSMB_1)
Y:$FFFF9B
ESAI_1/3 Receive Slot Mask Register A (RSMA_1)
Y:$FFFF9A
ESAI_1/3 Transmit Slot Mask Register B (TSMB_1)
Y:$FFFF99
ESAI_1/3 Transmit Slot Mask Register A (TSMA_1)
Y:$FFFF98
ESAI_1/3 Receive Clock Control Register (RCCR_1)
Y:$FFFF97
ESAI_1/3 Receive Control Register (RCR_1)
Y:$FFFF96
ESAI_1/3 Transmit Clock Control Register (TCCR_1)
Y:$FFFF95
ESAI_1/3 Transmit Control Register (TCR_1)
Y:$FFFF94
ESAI_1/3 Common Control Register (SAICR_1)
Y:$FFFF93
ESAI_1/3 Status Register (SAISR_1)
Y:$FFFF92
to
Y:$FFFF8C
Reserved
Y:$FFFF8B
ESAI_1/3 Receive Data Register 3 (RX3_1)
Y:$FFFF8A
ESAI_1/3 Receive Data Register 2 (RX2_1)
Y:$FFFF89
ESAI_1/3 Receive Data Register 1 (RX1_1)
Y:$FFFF88
ESAI_1/3 Receive Data Register 0 (RX0_1)
Y:$FFFF87
Reserved
Y:$FFFF86
ESAI_1/3 Time Slot Register (TSR_1/3)
Y:$FFFF85
ESAI_1/3 Transmit Data Register 5 (TX5_1)
Y:$FFFF84
ESAI_1/3 Transmit Data Register 4 (TX4_1)
Y:$FFFF83
ESAI_1/3 Transmit Data Register 3 (TX3_1)
Y:$FFFF82
ESAI_1/3 Transmit Data Register 2 (TX2_1)
Y:$FFFF81
ESAI_1/3 Transmit Data Register 1 (TX1_1)
Y:$FFFF80
ESAI_1/3 Transmit Data Register 0 (TX0_1)
ASRC
Y:$FF_FF7F
to
Y:$FF_FC1E
Reserved
Y: $FF_FC1D
Data Output Register for Pair C (ASRDOC)
Y: $FF_FC1C
Data Input Register for Pair C (ASRDIC)
Y: $FF_FC1B
Data Output Register for Pair B (ASRDOB)
Table 3-8. Detailed Device Y-Memory Map (Continued)
Peripherals
Address
Register Name
1