Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
19-4
Freescale Semiconductor
Asynchronous Sample Rate Converter
— Core master clock derivative (default is 5.644MHz, programmable through external module)
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The exchange of audio data is done by the DSP Core accessing the ASRC module through registers
defined on the Shared Peripheral bus.
19.1.3
Modes of Operation
In the description, many registers are used. The definition of the registers and parameters are described in
Section 19.2, “Memory Map and Register Definitions
19.1.3.1
Data Transfer Schemes
19.1.3.1.1
Data Input Modes
Three transfer modes are supported by ASRC: Mode 1 (Polling mode), Mode 2 (Interrupt mode), and
Mode 3 (DMA mode).
Mode 1 (Polling Mode)
After power on, reset (individually) or DSP clears ASRIER_ADIEx (where x = A, B or C), and ASRC
operates in Mode 1. In Polling mode, data input interrupts are disabled (ASRIERn_ADIEx=0, where
x = A, B or C). The DSP can poll ASRSTR_AIDEx to monitor input service requests.
The ASRC consumes data from each enabled input FIFO sample by sample, continually after each rising
edge of the input sampling clock. When the number of data words in every input FIFO is less than the
threshold, ASRC will set ASRSTR_AIDEx (x:A, B or C). After DSP checks the ASRSTR and finds these
input requests, the DSP will write enough data into the ASRDIA, ASRDIB or ASRDIC input register
accordingly, before the ASRC fetches the next data. When the ASRC fetches the next data, and if the
FIFOs are empty, an error will happen and ASRSTR_AOLE will be set.
The threshold of the input FIFOs is 32 samples (by default); the FIFO size of each channel is 64 samples.
All data should be written in a predefined sequence. If ASRDIA needs to be written, the sequence should
be: asrdi_0, asrdi_1, asrdi_2, asrdi_3, asrdi_0,asrdi_1, asrdi_2,..., asrdi_0, asrdi_1, asrdi_2, asrdi_3. Here
asrdi_n stands for the data intended for the nth channel. The hardware will re-allocate each data to its
corresponding channel FIFO. The channel being re-allocated is shown by ASRCCR_ACIA.
After the number of data in every input FIFO is greater than the threshold, the data-needed status bit will
be cleared.
Mode 2 (Interrupt Mode):
After DSP sets ASRIER_ADIEx (x=A, B or C), the input interrupt is enabled.
The ASRC consumes data from the input FIFO continually when it is working. When the number of data
words in the input FIFO is less than the threshold:
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The ASRC generates an interrupt request.
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A corresponding interrupt vector is transferred to the DSP.
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The status register’s corresponding bit ASRSTR_AIDEx (x:A, B or C) will be set.