Asynchronous Sample Rate Converter
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
19-5
To serve this request, the DSP should write enough data into the input FIFOs. When the ASRC fetches the
next data, and if the buffer is empty, an error will happen and ASRSTR_AOLE will be set. If the overload
interrupt is enabled, an overload interrupt will happen.
All data should be written in a predefined sequence too.
Mode 3 (DMA Mode):
ASRSTR_AIDEx (x = A, B or C) bits can also be used as DMA request source.
In DMA mode, when ASRSTR_AIDEx (x = A, B or C) is active, they will cause a DMA transfer. The
DMA-transferred data will feed into the ASRDIA, ASRDIB or ASRDIC input FIFOs. The other
requirements and behaviors of the DMA mode are the same as those in the polling mode.
19.1.3.1.2
Data Output Modes
Three transfer modes are supported by the Interface block.
Mode 1 (Polling Mode)
Output mode 1 is also a polling mode. It is almost the same as input mode 1, except that the direction of
data being transferred and the involved register bits are different. The threshold of the output FIFOs is 32
samples; the FIFO size of each channel is 64 samples.
Mode 2 (Interrupt Mode)
Output mode 2 is also an interrupt mode. It is almost the same as input mode 2, except that again the
direction of data being transferred and the involved register bits are different.
Mode 3 (DMA Mode)
Output mode 3 is also a DMA mode. It is almost the same as input mode 3, except that the direction of
data being transferred and the involved register bits are different.
19.2
Memory Map and Register Definitions
19.2.1
Memory Map
Table 19-2. Block Memory Map
Offset or
Address
Register
Access
Reset Value
Section/Page
0x0
ASRCTR
ASRC Control Register
R/W
0x00_0000
0x1
ASRIER
Interrupt Enable Register
R/W
0x00_0000
0x2
ASRIEM
Interrupt Enable Mask Register for both DSP cores
R/W
0x00_0000
0x3
ASRCNCR
Channel Number Configuration Register
R/W
0x00_0000
0x4
ASRCFG
Filter Configuration Status Register
R/W
0x00_0000