Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
18-14
Freescale Semiconductor
S/PDIF—Sony/Philips Digital Interface
18.2.7
S/PDIF FreqMeas Register (SRFM)
18.2.8
SPDIFTxClk Register (STC)
The SPDIFTxClk Control register includes the means to select the transmit clock and frequency division.
Address
X:$FFFF71
Access: User read
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FreqMeas
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-21. S/PDIF FreqMeas Register (SRFM)
Table 18-19. S/PDIF FreqMeas Register (SRFM) Fields
Bit
Field
Description
23–0
FreqMeas
Frequency measurement
Address X:$FFFF74
Access: User Read/Write
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
4’b0
SYSCLK_DF
TxClk_Source
0
TxClk_DF
W
Reset
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Figure 18-22. SPDIFTxClk Register (STC)
Table 18-20. SPDIFTxClk Register (STC) Fields
Bit
Field
Description
23–20
Reserved
Return zeros when read.
19–11
SYSCLK_DF
System Clock Divider Factor, 2–512.
9’d0
no clock signal
9’d1
divider factor is 2
...
9’d511 divider factor is 512
10–8
TxClk_Source 000 EXTAL input, 001: HCKT input,
010 HCKT1 input
011 HCKT2 input
100 HCKT3
101 Frequency divided system clock input