Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
21-92
Freescale Semiconductor
External Memory Controller (EMC)
programmed for SDRAM, only one chip select is active at any given time; thus, multiple chip selects can
share the same SDRAM machine.
21.5.3.2
Maximum Amount of SDRAM Supported
summarizes information based on SDRAM data sheets supplied by Micron.
The following examples use all 24 bits of the EMC. The 24-bit port size requires two SDRAM devices
(with 16-bit I/O ports) or three SDRAM devices (with 8-bit I/O port), all connected in parallel to a single
chip select.
21.5.3.3
Example of SDRAM Usage
This section shows examples of the use of EMC SDRAM machine.
21.5.3.3.1
Maximum Row Number Due to Bank Select MUX
SDMR[BSMA] is used to multiplex the bank select address. The BSMA field and corresponding
multiplexed address are shown below:
000 LA17–LA16
001 LA16–LA15
…
111 LA10–LA9
Note that LA17 is the latched value of LAD17.
The highest address pins that the bank selects can be multiplexed with, are LA[17:16], which limits the
pins for the row address to LA[15:0]. The EMC SDRAM machine supports 15 rows, which is sufficient
for all devices.
Table 21-74. Micron SDRAM Devices
SDRAM Devices
64 Mbit
128 Mbit
256 Mbit
I/O Port
x4
x8
x16
x32
x4
x8
x16
x32
x4
x8
x16
x32
Bank
4
4
4
4
4
4
4
4
4
4
4
4
Row
12
12
12
11
12
12
12
12
13
13
13
13
Column
10
9
8
8
11
10
9
8
11
10
9
8