Atmel SAM9X25, Manual

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8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The applica-
tion must set Mode to 5 in the Mode Register (see
Section 30.7.1 on page 452 ) and
perform a write access to the DDR2-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example,
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
DDR2-SDRAM write access should be done at the address 0x20400000.
An additional 200 cycles of clock are required for locking DLL
9. Program DLL field into the Configuration Register (see Section 30.7.3 on page 454 ) to
high (Enable DLL reset).
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
Mode to 3 in the Mode Register (see Section 30.7.1 on page 452 ) and perform a write
access to the DDR2-SDRAM to acknowledge this command. The write address must
be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
Section 30.7.1 on page 452 ). Perform a write access to any DDR2-
SDRAM address to acknowledge this command
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
Section 30.7.1 on page 452 ). Performs a write access to any DDR2-SDRAM loca-
tion twice to acknowledge these commands.
13. Program DLL field into the Configuration Register (see Section 30.7.3 on page 454 ) to
low (Disable DLL reset).
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-
SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see
Section 30.7.1 on page 452 )
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
15. Program OCD field into the Configuration Register (see Section 30.7.3 on page 454 ) to
high (OCD calibration default).
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The
application must set Mode to 5 in the Mode Register (see Section 30.7.1 on page 452 )
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
17. Program OCD field into the Configuration Register (see Section 30.7.3 on page 454 ) to
low (OCD calibration mode exit).
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The
application must set Mode to 5 in the Mode Register (see Section 30.7.1 on page 452 )
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.