Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
442
11054A–ATARM–27-Jul-11
SAM9X25
Figure 30-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access
30.5.4.2 Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
Low-power SDR-SDRAM and SDR-SDRAM devices. In the case of Low-power DDR1-SDRAM
devices, the controller generates a NOP command during a delay of at least TXP. In addition,
Low-power DDR1-SDRAM and DDR2-SDRAM must remain in power-down mode for a mini-
mum period of TCKE periods.
The exit procedure is faster than in self refresh mode. See Figure 30-22 on page 443 . The
DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout com-
mand bit.
• 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
• 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
• 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
NOP NOP PRCHALL MR S ARF S H NOP
0
Trfc
S DCLK
A[12:0]
COMMAND
CKE
BA[1:0]
2
NOP
Upd a te Extended mode
regi s ter
Trp
P as r-Tcr-D s
ACT
0
Tmrd