Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
758
11054A–ATARM–27-Jul-11
SAM9X25
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR ), the START
and STOP bits must be set at the same time. See Figure 38-9 . When a multiple data byte read is
performed, with or without internal address (IADR ), the STOP bit must be set after the next-to-
last data received. See Figure 38-10 . For Internal Address usage see Section 38.8.6 .
Figure 38-9. Master Read with One Data Byte
Figure 38-10. Master Read with Multiple Data Bytes
38.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
38.8.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 38-12 . See
Figure 38-11 and Figure 38-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
A S DADR R DATA N P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD
N
A S DADR R DATA n A A DATA (n+1) A DATA (n+m) DATA (n+m)-1 P TWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)