Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
34.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address: 0xF0008004 (0), 0xF000C004 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 660 .
• CLKDIV: Clock Divider
H i g h S p e e d M u l t i M e d i a C a r d I n t e r f a c e c l o c k ( M C C K o r H S M C I _ C K ) is M a s t e r C l o c k ( M C K ) d i v i d e r b y
({CLKDIV,2).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2
(PWSDIV)
+ 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN
bit).
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Read Proof.
1 = Enables Read Proof.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0 = Disables Write Proof.
1 = Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
0 = Disables Force Byte Transfer.
1 = Enables Force Byte Transfer.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – CLKODD
15 14 13 12 11 10 9 8
– PADV FBYTE WRPROOF RDPROOF PWSDIV
7 6 5 4 3 2 1 0
CLKDIV