Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
502
11054A–ATARM–27-Jul-11
SAM9X25
31.7 DMA Controller (DMAC) User Interface
Table 31-4. Register Mapping
Offset Register Name Access Reset
0x000 DMAC Global Configuration Register DMAC_GCFG Read-write 0x10
0x004 DMAC Enable Register DMAC_EN Read-write 0x0
0x008 DMAC Software Single Request Register DMAC_SREQ Read-write 0x0
0x00C DMAC Software Chunk Transfer Request Register DMAC_CREQ Read-write 0x0
0x010 DMAC Software Last Transfer Flag Register DMAC_LAST Read-write 0x0
0x014 Reserved
0x018
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Enable register.
DMAC_EBCIER Write-only –
0x01C
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Disable register.
DMAC_EBCIDR Write-only –
0x020
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Mask Register.
DMAC_EBCIMR Read-only 0x0
0x024
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Status Register.
DMAC_EBCISR Read-only 0x0
0x028 DMAC Channel Handler Enable Register DMAC_CHER Write-only –
0x02C DMAC Channel Handler Disable Register DMAC_CHDR Write-only –
0x030 DMAC Channel Handler Status Register DMAC_CHSR Read-only 0x00FF0000
0x034 Reserved – – –
0x038 Reserved – – –
0x03C+ch_num*(0x28)+(0x0) DMAC Channel Source Address Register DMAC_SADDR Read-write 0x0
0x03C+ch_num*(0x28)+(0x4) DMAC Channel Destination Address Register DMAC_DADDR Read-write 0x0
0x03C+ch_num*(0x28)+(0x8) DMAC Channel Descriptor Address Register DMAC_DSCR Read-write 0x0
0x03C+ch_num*(0x28)+(0xC) DMAC Channel Control A Register DMAC_CTRLA Read-write 0x0
0x03C+ch_num*(0x28)+(0x10) DMAC Channel Control B Register DMAC_CTRLB Read-write 0x0
0x03C+ch_num*(0x28)+(0x14) DMAC Channel Configuration Register DMAC_CFG Read-write 0x01000000
0x03C+ch_num*(0x28)+(0x18)
DMAC Channel Source Picture in Picture Configuration
Register
DMAC_SPIP Read-write 0x0
0x03C+ch_num*(0x28)+(0x1C)
DMAC Channel Destination Picture in Picture Configuration
Register
DMAC_DPIP Read-write 0x0
0x03C+ch_num*(0x28)+(0x20) Reserved – – –
0x03C+ch_num*(0x28)+(0x24) Reserved – – –
0x1E4 Write Protect Mode Register DMAC_WPMR Read-write 0x0
0x1E8 Write Protect Status Register DMAC_WPSR Read-only 0x0
0x01EC- 0x1FC Reserved – – –