464
11054A–ATARM–27-Jul-11
SAM9X25
464
11054A–ATARM–27-Jul-11
SAM9X25
30.7.9
DDRSDRC DLL Register
Name:
DDRSDRC_DLL
Address:
0xFFFFE824
Access:
Read-only
Reset:
The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time
and the data valid window.
• MDINC: DLL Master Delay Increment
0 = The DLL is not incrementing the Master delay counter.
1 = The DLL is incrementing the Master delay counter.
• MDDEC: DLL Master Delay Decrement
0 = The DLL is not decrementing the Master delay counter.
1 = The DLL is decrementing the Master delay counter.
• MDOVF
:
DLL Master Delay Overflow Flag
0 = The Master delay counter has not reached its maximum value, or the Master is not locked yet.
1 = The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL
forces the Master lock. If this flag is set, it means the DDRSDRC clock frequency is too low compared to Master delay line
number of elements.
• MDVAL
:
DLL Master Delay Value
Value of the Master delay counter.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
MDVAL
7
6
5
4
3
2
1
0
–
–
–
–
–
MDOVF
MDDEC
MDINC
Summary of Contents for SAM9X25
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Page 532: ...532 11054A ATARM 27 Jul 11 SAM9X25 532 11054A ATARM 27 Jul 11 SAM9X25...
Page 692: ...692 11054A ATARM 27 Jul 11 SAM9X25 692 11054A ATARM 27 Jul 11 SAM9X25...
Page 777: ...777 11054A ATARM 27 Jul 11 SAM9X25 777 11054A ATARM 27 Jul 11 SAM9X25...
Page 886: ...886 11054A ATARM 27 Jul 11 SAM9X25 886 11054A ATARM 27 Jul 11 SAM9X25...
Page 962: ...962 11054A ATARM 27 Jul 11 SAM9X25 962 11054A ATARM 27 Jul 11 SAM9X25...
Page 1036: ...1036 11054A ATARM 27 Jul 11 SAM9X25 1036 11054A ATARM 27 Jul 11 SAM9X25...
Page 1128: ...1128 11054A ATARM 27 Jul 11 SAM9X25 1128 11054A ATARM 27 Jul 11 SAM9X25...
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