438
11054A–ATARM–27-Jul-11
SAM9X25
438
11054A–ATARM–27-Jul-11
SAM9X25
Figure 30-15.
Burst Read Access, Latency = 3, DDR2-SDRAM Devices
Figure 30-16.
Burst Read Access, Latency = 2, SDR-SDRAM Devices
30.5.3
Refresh (Auto-refresh Command)
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh
cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that
the device is busy. A request of refresh does not interrupt a burst transfer in progress.
Col a
NOP
READ
NOP
0
Latency = 3
SDCLK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
D[15:0]
3
DM[1:0]
Latency = 2
SDCLK
col a
A[12:0]
NOP
READ
NOP
BST
NOP
COMMAND
0
BA[1:0]
DaDb
DcDd
DeDf
Dg Dh
D[31:0]
F
DM[3:0]
DQS[1:0]
Summary of Contents for SAM9X25
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