Atmel SAM9X25, Manual

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SAM9X25
– Unaligned system address to data transfer width supported in hardware
– Picture-In-Picture Mode (on DMAC0 only)
• Channel Buffering
– 16-word FIFO (64-word for channel 0 of DMAC0)
– Automatic packing/unpacking of data to fit FIFO width
• Channel Control
– Programmable multiple transaction size for each channel
– Support for cleanly disabling a channel without data loss
– Suspend DMA operation
– Programmable DMA lock transfer support
• Transfer Initiation
– Support for Software handshaking interface. Memory mapped registers can be used
to control the flow of a DMA transfer in place of a hardware handshaking interface
• Interrupt
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
completion, Single/Multiple transaction completion or Error condition
31.2.1 DMA Controller 0
• Two Masters
• Embeds 8 channels
• 64-byte FIFO for channel 0, 16-byte FIFO for Channels 1 to 7
• Features:
– Linked List support with Status Write Back operation at End of Transfer
– Word, HalfWord, Byte transfer support.
– Memory to Memory transfer
– Peripheral to memory
– Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals listed below. The hardware interface numbers are also given in
Table 31-1 .
Table 31-1. DMA Channel Definition
Instance Name T/R
DMA Channel HW
interface Number
HSMCI0 RX/TX 0
SPI0 TX 1
SPI0 RX 2
USART0 TX 3
USART0 RX 4
USART1 TX 5
USART1 RX 6
TWI0 TX 7