Atmel SAM9X25, Manual

Page: 520 / 1145

520
11054A–ATARM–27-Jul-11
SAM9X25
520
11054A–ATARM–27-Jul-11
SAM9X25
• SRC_DSCR: Source Address Descriptor
0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
• DST_DSCR: Destination Address Descriptor
0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.
• FC: Flow Control
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
• SRC_INCR
• DST_INCR
• IEN
If this bit is cleared, when the buffer transfer is completed, the BTC[x] flag is set in the EBCISR status register. This bit is
active low.
• AUTO: Automatic Multiple Buffer Transfer
0 (DISABLE): Automatic multiple buffer transfer is disabled.
1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several
buffers are transferred.
Value Name Description
000 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller
001 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller
010 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller
011 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller
Value Name Description
00 INCREMENTING The source address is incremented
01 DECREMENTING The source address is decremented
10 FIXED The source address remains unchanged
Value Name Description
00 INCREMENTING The destination address is incremented
01 DECREMENTING The destination address is decremented
10 FIXED The destination address remains unchanged