Atmel SAM9X25, Manual

Page: 1016 / 1145

1016
11054A–ATARM–27-Jul-11
SAM9X25
1016
11054A–ATARM–27-Jul-11
SAM9X25
44.9.3 SSC Receive Clock Mode Register
Name: SSC_RCMR
Address: 0xF0010010
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Receive Clock Selection
• CKO: Receive Clock Output Mode Selection
• CKI: Receive Clock Inversion
0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal
output is shifted out on Receive Clock rising edge.
1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – STOP START
7 6 5 4 3 2 1 0
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1 TK TK Clock signal
2 RK RK pin
3 Reserved
Value Name Description RK Pin
0 NONE None Input-only
1 CONTINUOUS Continuous Receive Clock Output
2 TRANSFER Receive Clock only during data transfers Output
3-7 Reserved