Atmel SAM9X25, Manual

Page: 494 / 1145

494
11054A–ATARM–27-Jul-11
SAM9X25
494
11054A–ATARM–27-Jul-11
SAM9X25
automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in
Table 31-3 on page 479 .
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number) then hardware does not stall until it detects a write to the buf-
fer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
Table 31-3 on page 479
before the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in Figure 31-13 on page 494 .
The DMAC Transfer flow is shown in Figure 31-14 on page 495 .
Figure 31-13. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
SADDR
Buffer0
Buffer1
Buffer2
DADDR(1)
DADDR(0)
DADDR(2)