Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
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11054A–ATARM–27-Jul-11
SAM9X25
46.13.2 Power-Up Sequence
Figure 46-2. VDDCORE and VDDIO Constraints at Startup
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that
these power sources reach their target values prior to the release of POR.
• VDDIOP must be
≥
V
ih
(refer to DC characteristics, Table 46-2 , for more details), (Tres + T1)
at the latest, after VDDCORE has reached
V
th+
.
• VDDIOM must reach V
OH
(refer to DC characteristics, Table 46-2 , for more details),
(Tres +T1 +T2) at the latest, after VDDCORE has reached
V
th+
– T
RES
is a POR characteristic
– T1 = 3 x T
SLCK
– T2 = 16 x T
SLCK
The T
SLCK
min (22 μs) is obtained for the maximum frequency of the internal RC oscillator
(44KHz).
– T
RES
= 30 μs
– T1 = 66 μs
– T2 = 352 μs
• VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled
into the ROM code.
As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to
ensure a reliable operation of the device.
46.14 SMC Timings
46.14.1 Timing Conditions
SMC Timings are given for MAX corners.
VDD (V)
Core Su pply POR O u tp u t
VDDIOtyp
Vih
Vth+
t
S LCK
<--- Tre s --->
VDDIO > Vih
VDDCORE
VDDIO
< T1 >
VDDCOREtyp
Voh
VDDIO > Voh
<------------ T2----------->