Atmel SAM9X25, Manual

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1102
11054A–ATARM–27-Jul-11
SAM9X25
1102
11054A–ATARM–27-Jul-11
SAM9X25
46.12 Analog-to-Digital Converter (ADC)
Note: 1. The Track-and-Hold Acquisition Time is given by:
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is given by:
The full speed is obtained for an input source impedance of < 50
Ω
maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this
Track and Hold Acquisition Time, also called Sampled and Hold Time.
Table 46-22. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Units
ADC Clock Frequency 10-bit resolution mode 13.2 MHz
Startup Time Return from Idle Mode 40 μs
Track and Hold Acquisition Time (TTH) ADC Clock = 13.2 MHz
(1)
0.5 μs
Conversion Time (TCT)
ADC Clock = 13.2 MHz
(1)
ADC Clock = 5 MHz
(1)
1.74
4.6
μs
Throughput Rate
ADC Clock = 13.2 MHz
(1)
ADC Clock = 5 MHz
(1)
440
192
kSPS
Table 46-23. External Voltage Reference Input
Parameter Conditions Min Typ Max Units
ADVREF Input Voltage Range 2.4 VDDANA V
ADVREF Average Current 600 μA
Current Consumption on VDDANA 600 μA
TTH (ns) 500 0.12 Z
IN
× ( ) Ω ( )
+ =
TCT μs
( )
23
Fclk
-----------
MHz
( )
=
Table 46-24. Analog Inputs
Parameter Min Typ Max Units
Input Voltage Range 0 ADVREF V
Input Leakage Current 2.5 mA
Input Capacitance 7 10 pF
Input Impedance 50
Ω