Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
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11054A–ATARM–27-Jul-11
SAM9X25
22. Power Management Controller (PMC)
22.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all sys-
tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the
peripherals and the Core.
22.2 Embedded Characteristics
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
• UPLLCK: From UTMI PLL
• PLLACK: From PLLA
• SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC oscillator
• MAINCK: Main Clock from external 12 MHz oscillator or internal 12 MHz RC Oscillator
PMC output clocks:
• Processor Clock PCK.
• Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge.
The divider can be 2, 3 or 4.
• Each peripheral embeds its own divider, programmable in the PMC User Interface.
• 266MHz DDR system clock
Note: DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
• USB Host EHCI High speed clock (UPLLCK)
• USB OHCI clocks (UHP48M and UHP12M)
• Two programmable clock outputs: PCK0 and PCK1
• SMD clock
This allows software control of five flexible operating modes:
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
stopped waiting for an interrupt
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery