Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
i. Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting
for request.
7. Wait for XFRDONE in HSMCI_SR register.
34.8.6 READ_SINGLE_BLOCK Operation using DMA Controller
34.8.6.1 Block Length is Multiple of 4
1. Wait until the current command execution has successfully completed.
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
5. Program HSMCI_DMA register with the following fields:
– ROPT field is set to 0.
– OFFSET field is set to 0.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
was previously set to false.
6. Issue a READ_SINGLE_BLOCK command.
7. Program the DMA controller.
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
reading the DMAC_EBCISR register.
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
the HSMCI_FIFO address.
e. The DMAC_DADDRx register for channel x must be word aligned.
f. Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
– DST_INCR is set to INCR.
– SRC_INCR is set to INCR.
– FC field is programmed with peripheral to memory flow control mode.
– both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
DMA controller is able to prefetch data and write HSMCI simultaneously.
h. Program DMAC_CFGx register for channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
HSMCI Host Controller.