Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the
Pin Description table.
4.2.1 Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with
mnemonics.
• “PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
• “I”/”O”
Indicates whether the signal is input or output state.
• “PU”/”PD”
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
• “ST”
Table 4-2. SAM9X25 I/O Type Assignment and Frequency
I/O Type
I/O Frequency
(MHz)
Charge Load
(pF)
Output
Current Signal Name
GPIO 40 10 all PIO lines except the following
GPIO_CLK 54 10
MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK,
EMACx_ETXCK, ISI_MCK
GPIO_CLK2 75 10
GPIO_ANA 25 10
16mA,
40mA (peak)
ADx, GPADx
EBI 133
50 (3.3V)
30 (1.8V)
all Data lines (Input/output) except the following
EBI_O 66
50 (3.3V)
30 (1.8V)
all Address and control lines (output only) except the
following
EBI_CLK 133 10 CK, #CK
RSTJTAG 10 10 NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
SYSC 0.25 10 WKUP, SHDN, JTAGSEL, TST, SHDN
VBG 0.25 10 VBG
USBFS 12 10
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
USBHS 480 10
HHSDPA, HHSDPB/DHSDP, HHSDMA,
HHSDMB/DHSDM
CLOCK 50 50 XIN, XOUT, XIN32, XOUT32
DIB 25 25 DIBN, DIBP