Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
405
11054A–ATARM–27-Jul-11
SAM9X25
29.13 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the Power Management Controller is asserted because MCK has
been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro-
grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is
provided so as to avoid reprogramming the User Interface with appropriate waveforms at very
slow clock rate. When activated, the slow mode is active on all chip selects.
29.13.1 Slow Clock Mode Waveforms
Figure 29-31 illustrates the read and write operations in slow clock mode. They are valid on all
chip selects. Table 29-5 indicates the value of read and write parameters in slow clock mode.
Figure 29-31. Read/write Cycles in Slow Clock Mode
A[ 25:2]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A [25:2]
MCK
NRD
NRD_CYCLE = 2
1
1
NCS
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NBS0, NBS1,
NBS2, NBS3,
A0,A1
Table 29-5. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP 1 NWE_SETUP 1
NRD_PULSE 1 NWE_PULSE 1
NCS_RD_SETUP 0 NCS_WR_SETUP 0
NCS_RD_PULSE 2 NCS_WR_PULSE 3
NRD_CYCLE 2 NWE_CYCLE 3