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533

11054A–ATARM–27-Jul-11

SAM9X25

533

11054A–ATARM–27-Jul-11

SAM9X25

33. USB High Speed Device Port (UDPHS)

33.1

Description

The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB),
rev 2.0 High Speed device specification.

Each endpoint can be configured in one of several USB transfer types. It can be associated with
one, two or three banks of a Dual-port RAM used to store the current data payload. If two or
three banks are used, one DPR bank is read or written by the processor, while the other is read
or written by the USB device peripheral. This feature is mandatory for isochronous endpoints.

33.2

Embedded Characteristics

• 1 Device High Speed

The High Speed USB Host Port A is shared with the High Speed USB Device port and con-
nected to the second UTMI transceiver. The selection between Host Port A and USB Device is
controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.

Figure 33-1.

USB Selection

• USB v2.0 High Speed Compliant, 480 Mbits Per Second

• UTMI Compliant

• 7 Endpoints

• Embedded Dual-port RAM for Endpoints

• Suspend/Resume Logic (Command of UTMI)

• Up to Three Memory Banks for Endpoints (Not for Control Endpoint)

• 4

KBytes of DPRAM

HS

Transceiver

DMA

HS USB Host

HS EHCI

FS OHCI

PB

PA

1

0

EN_UDPHS

PC

FS

Transceiver

HS

USB

Device

HS

Transceiver

DMA

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Summary of Contents for SAM9X25

Page 1: ...h dedicated programmable clock for best performance Two dual port 8 channel DMA Controllers Advanced Interrupt Controller and Debug Unit Two Programmable External Clock Signals Low Power Mode Shut Dow...

Page 2: ...inter faces include a soft modem supporting exclusively the Conexant SmartDAA line driver HS USB Device and Host FS USB Host two HS SDCard SDIO MMC interfaces USARTs SPIs I2S TWIs and 10 bit ADC To e...

Page 3: ...l 10 bit ADC ADVREF VDDANA AD5 AD11 AD0 AD1 AD2 AD3 PIO PWM AD4 Peripheral Bridge SRAM 32KB Peripheral Bridge TK TF TD RD RF RK PC FS Transc HFSDPC HFSDMC 8 CH DMA 8 CH DMA PW M 0 PW M 3 GNDANA UTXD0...

Page 4: ...trol Output WKUP Wake Up Input Input ICE and JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out Output TMS Test Mode Select Input JTAGSEL JTAG Selection Input RTCK Return Test Clock Ou...

Page 5: ...e Enable Output Low DDR2 SDRAM LPDDR Controller SDCK SDCK DDR2 SDRAM Differential Clock Output SDCKE DDR2 SDRAM Clock Enable Output High SDCS DDR2 SDRAM Controller Chip Select Output Low BA 0 2 Bank S...

Page 6: ...TK SSC Transmit Clock I O RK SSC Receive Clock I O TF SSC Transmit Frame Sync I O RF SSC Receive Frame Sync I O Timer Counter TCx x 0 5 TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x...

Page 7: ...ort UDPHS DFSDM USB Device Full Speed Data Analog DFSDP USB Device Full Speed Data Analog DHSDM USB Device High Speed Data Analog DHSDP USB Device High Speed Data Analog Ethernet 10 100 EMAC0 ETXCK Tr...

Page 8: ...Output I O Analog to Digital Converter ADC AD0 AD11 12 Analog Inputs Analog ADTRG ADC Trigger Input ADVREF ADC Reference Analog CAN Controller CANx CANRXx CAN input Input CANTXx CAN output Output Sof...

Page 9: ...ype Description I O Type Voltage Range Analog Pull up Pull down Schmitt Trigger GPIO 1 65 3 6V switchable switchable switchable GPIO_CLK 1 65 3 6V switchable switchable switchable GPIO_CLK2 1 65 3 6V...

Page 10: ...lar the address lines which require the pin to be driven as soon as the reset is released I O Indicates whether the signal is input or output state PU PD Indicates whether Pull Up Pull Down or nothing...

Page 11: ...le The PB18 Reset State column shows PIO I PU ST That means the line PIO18 is configured as an Input with Pull Up and Schmitt Trigger enabled PD14 reset state is PIO I PU That means PIO Input with Pul...

Page 12: ...P0 GPIO PA15 I O MCI0_DA0 I O PIO I PU ST P5 VDDIOP0 GPIO PA16 I O MCI0_CDA I O PIO I PU ST R5 VDDIOP0 GPIO_CLK PA17 I O MCI0_CK I O PIO I PU ST U5 VDDIOP0 GPIO PA18 I O MCI0_DA1 I O PIO I PU ST T5 VD...

Page 13: ...I PU ST G2 VDDIOP1 GPIO PC10 I O PWM0 O PIO I PU ST H3 VDDIOP1 GPIO PC11 I O PWM1 O PIO I PU ST J3 VDDIOP1 GPIO PC12 I O TIOA5 I O PIO I PU ST L2 VDDIOP1 GPIO PC13 I O TIOB5 I O PIO I PU ST H1 VDDIOP1...

Page 14: ...NF EBI PD17 I O D27 O A24 O A24 O PD K17 VDDNF EBI PD18 I O D28 O A25 O A25 O PD J17 VDDNF EBI PD19 I O D29 O NCS2 O PIO I PU K16 VDDNF EBI PD20 I O D30 O NCS4 O PIO I PU J16 VDDNF EBI PD21 I O D31 O...

Page 15: ...A3 O O PD G17 VDDIOM EBI_O A4 O O PD G16 VDDIOM EBI_O A5 O O PD F17 VDDIOM EBI_O A6 O O PD E17 VDDIOM EBI_O A7 O O PD F16 VDDIOM EBI_O A8 O O PD G15 VDDIOM EBI_O A9 O O PD G14 VDDIOM EBI_O A10 O O PD...

Page 16: ...R17 VDDUTMII USBHS HHSDPB I O O PD P17 VDDUTMII USBHS HHSDMB I O O PD L17 VDDUTMII USBFS HFSDPC I O O PD M17 VDDUTMII USBFS HFSDMC I O O PD R11 VDDIOP0 DIB DIBN I O O PU P11 VDDIOP0 DIB DIBP I O O PU...

Page 17: ...lines GNDIOM VDDNF 1 65 1 95V 1 8V 3 0 3 6V 3 3V NAND Flash I O and control D16 D32 and multiplexed SMC lines GNDIOM VDDIOP0 1 65 3 6V a part of Peripheral I O lines 1 GNDIOP VDDIOP1 1 65 3 6V a part...

Page 18: ...000 0xF000 4000 SMD 0xF805 0000 ADC 0xFFFF FE00 0xFFFF FC00 0xFFFF EC00 0xFFFF EA00 0xFFFF E800 0xFFFF E600 0xFFFF E000 16 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes PMC PIOC PIOB PIOA DB...

Page 19: ...speed SRAM After reset and until the Remap Command is performed the SRAM is only accessible at address 0x0030 0000 After Remap the SRAM also becomes available at address 0x0 6 2 2 Internal ROM The SA...

Page 20: ...h DDR2 LPDDR with 16 bit Data Path One Chip Select for SDRAM Device 256 Mbyte Address Space Programming Facilities Multibank Ping pong Access Up to 8 Banks Opened at Same Time Reduces Average Latency...

Page 21: ...d voltage range for external memories The System Controller s peripherals are all mapped within the highest 16 KBytes of address space between addresses 0xFFFF C000 and 0xFFFF FFFF However all the reg...

Page 22: ...d pit_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq SLCK Boundary Scan TAPController jtag_nreset debug PCK debug idle debug BusMatrix MCK periph_nreset proc_nreset periph_nreset idle Debug Unit dbgu_...

Page 23: ...0x0792_603F 7 2 Backup Section The SAM9X25 features a Backup Section that embeds RC Oscillator Slow Clock Oscillator Real Time Counter RTC Shutdown Controller 4 Backup Registers Slow Clock Control Reg...

Page 24: ...pheral Identifiers Instance ID Instance Name Instance Description External interrupt Wired OR interrupt 0 AIC Advanced Interrupt Controller FIQ 1 SYS System Controller Interrupt DBGU PMC SYSC PMECC PM...

Page 25: ...e of three peripheral functions A B or C Refer to Section 4 Package and Pinout Table 4 3 to see the PIO assignments 22 UHPHS USB Host High Speed 23 UDPHS USB Device High Speed 24 EMAC0 Ethernet MAC0 2...

Page 26: ...26 11054A ATARM 27 Jul 11 SAM9X25...

Page 27: ...reless and embedded devices It includes an enhanced multiplier design for improved DSP performance The ARM926EJ S processor supports the ARM debug architecture and includes logic to assist in both har...

Page 28: ...ies One Address Entry Software Control Drain Memory Management Unit MMU Access Permission for Sections Access Permission for Large Pages and Small Pages 16 Embedded Domains 64 Entry Instruction TLB an...

Page 29: ...rocessor External Coprocessor Interface Trace Port Interface ARM9EJ S Processor Core DTCM Interface Data TLB Instruction TLB ITCM Interface Data Cache AHB Interface and Write Buffer Instruction Cache...

Page 30: ...lock cycles Execute Memory and Writeback stages 9 4 4 Memory Access The ARM9EJ S core supports byte 8 bit half word 16 bit and word 32 bit access Words must be aligned to four byte boundaries half wor...

Page 31: ...system Abort mode is entered after a data or instruction prefetch abort System mode is a privileged user mode for the operating system Undefined mode is entered when an undefined instruction exception...

Page 32: ...ther reg ister called Saved Program Status Register SPSR that becomes available in privileged modes instead of CPSR This register contains condition code flags and the current mode bits saved as a res...

Page 33: ...when set by an instruction it remains set until explicitly cleared by an MSR instruction writing to the CPSR Instructions cannot execute conditionally on the status of the Q flag The J bit in the CPS...

Page 34: ...rent PC r15 4 or PC 8 depending on the exception THUMB state the ARM9EJ S writes the value of the PC into LR offset by a value current PC 2 PC 4 or PC 8 depending on the exception that causes the prog...

Page 35: ...ions can be executed conditionally Every instruction contains a 4 bit condition code field bits 31 28 For further details see the ARM Technical Reference Manual Table 9 2 gives the ARM instruction mne...

Page 36: ...sor CDP Coprocessor Data Processing Table 9 2 ARM Instruction Mnemonic List Continued Mnemonic Operation Mnemonic Operation Table 9 3 New ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Oper...

Page 37: ...n Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logi...

Page 38: ...0 ID Code 1 Read Unpredictable 0 Cache type 1 Read Unpredictable 0 TCM status 1 Read Unpredictable 1 Control Read write 2 Translation Table Base Read write 3 Domain Access Control Read write 4 Reserve...

Page 39: ...details refer to CP15 spe cific register behavior opcode_2 7 5 Determines specific coprocessor operation code By default set to 0 Rd 15 12 ARM Register Defines the ARM register whose value is transfe...

Page 40: ...k aside Buffer TLB Translation table walk hardware 9 6 1 Access Control Logic The access control logic controls access information for every entry in the translation table The access control logic che...

Page 41: ...tains status and address information about faults generated by the data accesses in the data fault status register and fault address register It also retains the status of faults generated by instruct...

Page 42: ...checks Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface If the MMU is disabled all data accesses are noncachable nonbufferable wit...

Page 43: ...those in the external memory When a cache write miss occurs a line chosen by round robin or another algorithm is stored in the write buffer which transfers it to external memory 9 8 Bus Interface Uni...

Page 44: ...ddresses to the necessary boundary 16 bit accesses are aligned to halfword boundaries and 32 bit accesses are aligned to word boundaries Table 9 7 Supported Transfers HBurst 2 0 Description SINGLE Sin...

Page 45: ...interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica tion Channel A set of dedicated debug and test input output pins gives direct access to the...

Page 46: ...A ATARM 27 Jul 11 SAM9X25 10 3 Block Diagram Figure 10 1 Debug and Test Block Diagram ICE RT ARM9EJ S DMA DBGU PIO DRXD DTXD TMS TCK TDI JTAGSEL TDO TST Reset and Test TAP Test Access Port Boundary Po...

Page 47: ...dard debugging functions such as downloading code and single stepping through the pro gram A software debugger running on a personal computer provides the user interface for configuring a Trace Port i...

Page 48: ...re sent and interpreted by the tes ter In this example the board in test is designed using a number of JTAG compliant devices These devices can be connected to form a single scan chain Figure 10 3 App...

Page 49: ...Level Reset Test NRST Microcontroller Reset Input Output Low TST Test Mode Select Input High ICE and JTAG NTRST Test Reset Signal Input Low TCK Test Clock Input TDI Test Data In Input TDO Test Data Ou...

Page 50: ...I 0222A 10 6 3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine TDI is the Test Data Input line which supplies the data to t...

Page 51: ...erface A specific register the Debug Unit Chip ID Register gives information about the product version and its internal configuration The device Debug Unit Chip ID value is 0x819A_05A1 on 32 bit width...

Page 52: ...PART NUMBER 27 12 Product Part Number Product part Number is 0x5B2F MANUFACTURER IDENTITY 11 1 Set to 0x01F Bit 0 required by IEEE Std 1149 1 Set to 0x1 JTAG ID Code value is 0x05B2_F03F 31 30 29 28 2...

Page 53: ...ers The user software in the external memory performs a complete configuration Enable the 32 768 Hz oscillator if best accuracy is needed Program the PMC main oscillator enable or bypass mode Program...

Page 54: ...quartz detection This detection is successful when the MOSCXTS and MOSCSELS bits rise else the 12 MHz Fast RC internal oscillator is used as the Main Clock 3 Main Clock Selection the Master Clock sou...

Page 55: ...nce Register BSCR The 3 LSBs of the BSCR are available to control the sequence The user can then choose to bypass some steps shown in Figure 11 2 NVM Bootloader Sequence Diagram according to the BSCR...

Page 56: ...EEPROM Boot Y es NAND Flash Boot Copy from NAND Flash to SRAM Run Y es NAND Flash Bootloader No SD Card Boot Copy from SD Card to SRAM Run Y es SD Card Bootloader No Device Setup No No SAM BA Monitor...

Page 57: ...ce If the initialization is successful the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains valid code If the NVM does not contain valid code the NVM bootloader...

Page 58: ...s and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors Except for the sixth vector these bytes must implement the ARM instructions for either branch or load PC with P...

Page 59: ...gram must be a file named boot bin written in the root directory of the filesystem Its size must not exceed the maximum size allowed 24 kbytes 0x6000 11 4 4 Detailed Memory Boot Procedures 11 4 4 1 NA...

Page 60: ...meters from the header Read NAND Flash and PMECC parameters from the ONFI Restore the reset values for the peripherals Perform the REMAP and set the PC to 0 to jump to the downloaded application Initi...

Page 61: ...ot use PMECC to detect and correct the data 1 Use PMECC to detect and correct the data nbSectorPerPage Number of sectors per page spareSize Size of the spare zone in bytes eccBitReq Number of ECC bits...

Page 62: ...AM Note Booting on 16 bit NAND Flash is not possible only 8 bit NAND Flash memories are supported 11 4 4 2 NAND Flash Boot PMECC Error Detection and Correction NAND Flash boot procedure uses PMECC to...

Page 63: ...ze unsigned int sectorSize 0 for 512 1 for 1024 bytes unsigned int errBitNbrCapability unsigned int eccSizeByte unsigned int eccStartAddr unsigned int eccEndAddr unsigned int nandWR unsigned int spare...

Page 64: ...ted SD Card Devices SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2 0 This includes SDHC cards 11 4 4 4 SPI Flash Boot Two kinds of SPI Flash are supported SP...

Page 65: ...ripheral mode to communicate with external memory devices Care must be taken when these PIOs are used by the application The devices con nected could be unintentionally driven at boot time and electri...

Page 66: ...GU Once the communication interface is identified the application runs in an infinite loop waiting for different commands as listed in Table 11 4 Table 11 3 PIO Driven during Boot Program Execution NV...

Page 67: ...t Character s received on DBGU Run monitor Wait for command on the USB link Run monitor Wait for command on the DBGU link USB Enumeration Successful Yes Yes No No Init DBGU and USB No valid code in NV...

Page 68: ...to 115 200 Baud 8 bits of data no parity 1 stop bit 11 5 2 1 Supported External Crystal External Clocks The SAM BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external...

Page 69: ...is Atmel s vendor ID 0x03EB The product ID is 0x6124 These references are used by the host operating system to mount the correct driver On Windows systems the INF files contain the correspondence betw...

Page 70: ...to several data payloads by the host driver If the command requires a response the host can send IN transactions to pick up the response GET_STATUS Returns status for the specified recipient SET_FEATU...

Page 71: ...s ter BSCR This register is powered by VDDBU the modification is saved and applied after the next reset The register is taking Factory Value in case of battery removing This register is programmable w...

Page 72: ...FFFFFE54 Access Read write Factory Value 0x0000_0000 BOOTx Boot media sequence Is defined in the product dependent ROM code BOOTKEY 0xB5 VALID valid boot key To avoid spurious writing this key is nece...

Page 73: ...r external interrupt source to provide a fast inter rupt rather than a normal interrupt 13 2 Embedded Characteristics Controls the Interrupt Lines nIRQ and nFIQ of an ARM Processor Thirty two Individu...

Page 74: ...ded Up to Thirty two Sources nFIQ nIRQ Advanced Interrupt Controller Embedded Peripherals External Peripherals External Interrupts Standalone Applications RTOS Drivers Hard Real Time Tasks OS based Ap...

Page 75: ...ource 0 cannot be used The Interrupt Source 1 is always located at System Interrupt This is the result of the OR wiring of the system peripheral interrupt lines When a system interrupt occurs the serv...

Page 76: ...gisters Clear ing or setting interrupt sources programmed in level sensitive mode has no effect The clear operation is perfunctory as the software must perform an action to reinitialize the memorizati...

Page 77: ...nput Stage Edge Detector Clear Set Source i AIC_IPR AIC_IMR AIC_IECR AIC_IDCR AIC_ISCR AIC_ICCR Fast Interrupt Controller or Priority Controller FF Level Edge AIC_SMRI SRCTYPE Edge Detector Clear Set...

Page 78: ...pt edge or level or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro cessor The resynchronization time depends on the programming of the interrupt so...

Page 79: ...a new interrupt condition might have hap pened on other interrupt sources since the nIRQ has been asserted the priority controller determines the current interrupt at the time the AIC_IVR Interrupt Ve...

Page 80: ...g to the cur rent interrupt is returned This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt as AIC_IVR is mapped at the absolute address...

Page 81: ...nto the program counter at the end of the interrupt For example the instruction SUB PC LR 4 may be used 5 Further interrupts can then be unmasked by clearing the I bit in CPSR allowing re assertion of...

Page 82: ...at the absolute address 0xFFFF F104 and thus accessible from the ARM fast inter rupt vector at address 0x0000 001C through the following instruction LDR PC PC F20 When the processor executes this ins...

Page 83: ...r 0x1C This method does not use the vectoring so that reading AIC_FVR must be performed at the very beginning of the handler operation However this method saves the execution of a branch instruction 1...

Page 84: ...d of Interrupt command is necessary to acknowledge and to restore the context of the AIC This operation is generally not performed by the debug system as the debug system would become strongly intrusi...

Page 85: ...ive level occurs for only a short time An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time As in...

Page 86: ...rite access in a write protected register is detected then the WPVS flag in the AIC Write Protect Status Register AIC_WPSR is set and the WPVSRC field indicates in which register the write access has...

Page 87: ...ector Register 31 AIC_SVR31 Read write 0x0 0x100 Interrupt Vector Register AIC_IVR Read only 0x0 0x104 FIQ Interrupt Vector Register AIC_FVR Read only 0x0 0x108 Interrupt Status Register AIC_ISR Read...

Page 88: ...interrupt sources 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCTYPE PRIOR Value Name Description 0 LOWEST Lowest priority for the corresponding interrupt 7...

Page 89: ...d write Reset 0x0 This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register VECTOR Source Vector The user may store in these registers the addresses of the corres...

Page 90: ...tains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt The Source Vector Register is indexed using the current interrupt number when the Interrupt...

Page 91: ...Read only Reset 0x0 FIQV FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 When there is no fast interrupt the FIQ Vector Register...

Page 92: ...errupt Status Register Name AIC_ISR Address 0xFFFFF108 Access Read only Reset 0x0 IRQID Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number 31 30 29...

Page 93: ...k 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID...

Page 94: ...us Register Name AIC_CISR Address 0xFFFFF114 Access Read only Reset 0x0 NFIQ NFIQ Status 0 nFIQ line is deactivated 1 nFIQ line is active NIRQ NIRQ Status 0 nIRQ line is deactivated 1 nIRQ line is act...

Page 95: ...ite only FIQ SYS PID2 PID31 Interrupt Enable 0 No effect 1 Enables corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 P...

Page 96: ...ite only FIQ SYS PID2 PID31 Interrupt Disable 0 No effect 1 Disables corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22...

Page 97: ...rite only FIQ SYS PID2 PID31 Interrupt Clear 0 No effect 1 Clears corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PI...

Page 98: ...Write only FIQ SYS PID2 PID31 Interrupt Set 0 No effect 1 Sets corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21...

Page 99: ...rite only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete Any value can be written because it is only necessary to make a wr...

Page 100: ...if the WPEN bit is cleared in AIC Write Protect Mode Register SIVR Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register The written value...

Page 101: ...written if the WPEN bit is cleared in AIC Write Protect Mode Register PROT Protection Mode 0 The Protection Mode is disabled 1 The Protection Mode is enabled GMSK General Mask 0 The nIRQ and nFIQ line...

Page 102: ...D2 PID31 Fast Forcing Enable 0 No effect 1 Enables the fast forcing feature on the corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17...

Page 103: ...D2 PID31 Fast Forcing Disable 0 No effect 1 Disables the Fast Forcing feature on the corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 1...

Page 104: ...The Fast Forcing feature is disabled on the corresponding interrupt 1 The Fast Forcing feature is enabled on the corresponding interrupt 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID...

Page 105: ...f WPKEY corresponds to 0x414943 AIC in ASCII Protects the registers AIC Source Mode Register on page 88 AIC Source Vector Register on page 89 AIC Spurious Interrupt Vector Register on page 100 AIC Deb...

Page 106: ...on has occurred since the last read of the AIC_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Wr...

Page 107: ...tly or simultaneously the external reset and the peripheral and processor resets 14 2 Embedded Characteristics Manages All Resets of the System Including External Devices Through the NRST Pin Processo...

Page 108: ...ls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required The NRST Manager shapes the NRST assertion during a programmable time thus co...

Page 109: ..._SR is read 14 4 3 1 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin When this occurs the nrst_out signal is driven low by the NRST Manager for...

Page 110: ...s hardcoded to comply with the Slow Clock Oscillator startup time After this time the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor...

Page 111: ...M processor At the end of this delay the processor and other reset signals rise The field RSTTYP in RSTC_SR is updated to report a Wake up Reset The nrst_out remains asserted for EXTERNAL_RESET_LENGTH...

Page 112: ...abled as soon as NRST is confirmed high When the processor reset signal is released the RSTTYP field of the Status Register RSTC_SR is loaded with the value 0x4 indicating a User Reset The NRST Manage...

Page 113: ...defined by the field ERSTL in the Mode Register RSTC_MR The software reset is entered if at least one of these bits is set by the software All these com mands can be performed independently or simult...

Page 114: ...d the Peripheral Reset are asserted The NRST line is also asserted depending on the programming of the field ERSTL However the resulting low level on NRST does not result in a User Reset state If WDRP...

Page 115: ...event is impossible because the Watchdog Timer is being reset by the proc_nreset signal A software reset is impossible since the processor reset is being activated When in Software Reset A watchdog e...

Page 116: ...he current one This bit is automatically cleared at the end of the current software reset NRSTL bit The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge...

Page 117: ...ue of RSTC_SR either reports a General Reset or a Wake up Reset depending on last rising power supply Table 14 1 Register Mapping Offset Register Name Access Reset Back up Reset 0x00 Control Register...

Page 118: ...s correct resets the processor PERRST Peripheral Reset 0 No effect 1 If KEY is correct resets the peripherals EXTRST External Reset 0 No effect 1 If KEY is correct asserts the NRST pin KEY Password Sh...

Page 119: ...l Registers the NRST Pin Level at Master Clock MCK SRCMP Software Reset Command in Progress 0 No software command is being performed by the reset controller The reset controller is ready for a softwar...

Page 120: ...ld defines the external reset length The external reset is asserted during a time of 2 ERSTL 1 Slow Clock cycles This allows assertion duration to be programmed between 60 s and 2 seconds KEY Password...

Page 121: ...be 24 hour mode or 12 hour mode with an AM PM indicator Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32 bit data bus An entry control i...

Page 122: ...y 4 being leap years This is correct up to the year 2099 15 5 1 Reference Clock The reference clock is Slow Clock SLCK It can be driven internally or by an external 32 768 kHz crystal During low power...

Page 123: ...r value can be pro grammed and the returned value on RTC_TIME will be the corresponding 24 hour value The entry control checks the value of the AM PM indicator bit 22 of RTC_TIME register to determine...

Page 124: ...2 Update Sequence Prepare TIme or Calendar Fields Set UPDTIM and or UPDCAL bit s in RTC_CR Read RTC_SR ACKUPD 1 Clear ACKUPD bit in RTC_SCCR Update Time and or Calendar values in RTC_TIMR RTC_CALR Cle...

Page 125: ...egister RTC_TIMR Read write 0x0 0x0C Calendar Register RTC_CALR Read write 0x01210720 0x10 Time Alarm Register RTC_TIMALR Read write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read write 0x01010000 0...

Page 126: ...counters Calendar counters can be programmed once this bit is set TIMEVSEL Time Event Selection The event that generates the flag TIMEV in RTC_SR Status Register depends on the value of TIMEVSEL CALE...

Page 127: ...6 2 RTC Mode Register Name RTC_MR Address 0xFFFFFEB4 Access Read write HRMOD 12 24 hour Mode 0 24 hour mode is selected 1 12 hour mode is selected All non significant bits read zero 31 30 29 28 27 26...

Page 128: ...ns MIN Current Minute The range that can be set is 0 59 BCD The lowest four bits encode the units The higher bits encode the tens HOUR Current Hour The range that can be set is 1 12 BCD in 12 hour mod...

Page 129: ...ns MONTH Current Month The range that can be set is 01 12 BCD The lowest four bits encode the units The higher bits encode the tens DAY Current Day in Current Week The range that can be set is 1 7 BCD...

Page 130: ...is the alarm field corresponding to the BCD coded minute counter MINEN Minute Alarm Enable 0 The minute matching alarm is disabled 1 The minute matching alarm is enabled HOUR Hour Alarm This field is...

Page 131: ...BCD coded month counter MTHEN Month Alarm Enable 0 The month matching alarm is disabled 1 The month matching alarm is enabled DATE Date Alarm This field is the alarm field corresponding to the BCD co...

Page 132: ...TIMEV Time Event 0 No time event has occurred since the last clear 1 At least one time event has occurred since the last clear The time event is selected in the TIMEVSEL field in RTC_CR Control Regist...

Page 133: ...o effect 1 Clears corresponding status flag in the Status Register RTC_SR SECCLR Second Clear 0 No effect 1 Clears corresponding status flag in the Status Register RTC_SR TIMCLR Time Clear 0 No effect...

Page 134: ...larm Interrupt Enable 0 No effect 1 The alarm interrupt is enabled SECEN Second Event Interrupt Enable 0 No effect 1 The second periodic interrupt is enabled TIMEN Time Event Interrupt Enable 0 No eff...

Page 135: ...Interrupt Disable 0 No effect 1 The alarm interrupt is disabled SECDIS Second Event Interrupt Disable 0 No effect 1 The second periodic interrupt is disabled TIMDIS Time Event Interrupt Disable 0 No e...

Page 136: ...rupt is disabled 1 The alarm interrupt is enabled SEC Second Event Interrupt Mask 0 The second periodic interrupt is disabled 1 The second periodic interrupt is enabled TIM Time Event Interrupt Mask 0...

Page 137: ...d in RTC_CALR Calendar Register 1 RTC_CALR has contained invalid data since it was last programmed NVTIMALR Non valid Time Alarm 0 No invalid data has been detected in RTC_TIMALR Time Alarm Register 1...

Page 138: ...138 11054A ATARM 27 Jul 11 SAM9X25 138 11054A ATARM 27 Jul 11 SAM9X25...

Page 139: ...e time 16 2 Embedded Characteristics 20 bit Programmable Counter plus 12 bit Interval Counter Reset on read Feature Both Counters Work on Master Clock 16 Real Time OS or Linux WinCE compliant tick gen...

Page 140: ...nters When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register PIT_PIVR the overflow counter PICNT is reset and the PITS is cleared thus acknowledging the interrupt The...

Page 141: ...X25 141 11054A ATARM 27 Jul 11 SAM9X25 Figure 16 2 Enabling Disabling PIT with PITEN MCK Prescaler PIV PIV 1 0 PITEN 1 0 0 15 CPIV 1 restarts MCK Prescaler 0 1 APB cycle read PIT_PIVR 0 PICNT PITS PIT...

Page 142: ...Interface Table 16 1 Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read write 0x000F_FFFF 0x04 Status Register PIT_SR Read only 0x0000_0000 0x08 Periodic Interval Value...

Page 143: ...eriodic Interval Timer CPIV The period is equal to PIV 1 PITEN Period Interval Timer Enabled 0 The Periodic Interval Timer is disabled when the PIV value is reached 1 The Periodic Interval Timer is en...

Page 144: ...SR Address 0xFFFFFE34 Access Read only PITS Periodic Interval Timer Status 0 The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR 1 The Periodic Interval timer has reached P...

Page 145: ...ading this register clears PITS in PIT_SR CPIV Current Periodic Interval Value Returns the current value of the periodic interval timer PICNT Periodic Interval Counter Returns the number of occurrence...

Page 146: ...3C Access Read only CPIV Current Periodic Interval Value Returns the current value of the periodic interval timer PICNT Periodic Interval Counter Returns the number of occurrences of periodic interval...

Page 147: ...mode 17 2 Embedded Features 16 bit Key protected only once Programmable Counter Provides Reset or Interrupt Signals to the System Windowed prevents the processor to be in a dead lock on the watchdog...

Page 148: ...ter is write protected As a result writing WDT_CR without the correct hard coded key has no effect If an underflow does occur the wdt_fault signal to the Reset Controller is asserted if the bit WDRSTE...

Page 149: ...n idle mode the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR Figure 17 2 Watchdog Behavior 0 WDV WDD WDT_CR WDRSTT Watchdog Fault Normal b...

Page 150: ...l 11 SAM9X25 17 5 Watchdog Timer WDT User Interface Table 17 1 Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write only 0x04 Mode Register WDT_MR Read write Once 0x3F...

Page 151: ...e WDT_CR Address 0xFFFFFE40 Access Write only WDRSTT Watchdog Restart 0 No effect 1 Restarts the Watchdog KEY Password Should be written at value 0xA5 Writing any other value in this field aborts the...

Page 152: ...activates all resets 1 If WDRSTEN is 1 a Watchdog fault underflow or error activates the processor reset WDD Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer If the W...

Page 153: ...153 11054A ATARM 27 Jul 11 SAM9X25 153 11054A ATARM 27 Jul 11 SAM9X25 0 Enables the Watchdog Timer 1 Disables the Watchdog Timer...

Page 154: ...No Watchdog underflow occurred since the last read of WDT_SR 1 At least one Watchdog underflow occurred since the last read of WDT_SR WDERR Watchdog Error 0 No Watchdog error occurred since the last...

Page 155: ...Assertion of the SHDW Output Pin Programmable De assertion from the WKUP Input Pins AMBA compliant Interface Interfaces to the ARM Advanced Peripheral Bus 18 3 Block Diagram Figure 18 1 Shutdown Cont...

Page 156: ...the DC DC Converter pro viding the main power supplies of the system and especially VDDCORE and or VDDIO The wake up inputs WKUP0 connect to any push buttons or signal that wake up the system The soft...

Page 157: ...he counter reaches the value programmed in the corresponding field CPTWK0 the SHDN pin is released If a new input change is detected before the counter reaches the corre sponding value the counter is...

Page 158: ...7 Shutdown Controller SHDWC User Interface Table 18 2 Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write only 0x04 Shutdown Mode Register SHDW_MR Read writ...

Page 159: ...Address 0xFFFFFE10 Access Write only SHDW Shutdown Command 0 No effect 1 If KEY is correct asserts the SHDN pin KEY Password Should be written at value 0xA5 Writing any other value in this field abort...

Page 160: ...ternal synchronization of WKUP0 the SHDN pin is released CPTWK x 16 1 Slow Clock cycles after the event on WKUP RTCWKEN Real time Clock Wake up Enable 0 The RTC Alarm signal has no effect on the Shutd...

Page 161: ...up input since the last read of SHDW_SR 1 At least one wake up event occurred on the corresponding wake up input since the last read of SHDW_SR RTCWK Real time Clock Wake up 0 No wake up alarm from t...

Page 162: ...162 11054A ATARM 27 Jul 11 SAM9X25 162 11054A ATARM 27 Jul 11 SAM9X25...

Page 163: ...ds Four general purpose backup registers 19 2 Embedded Characteristics Four 32 bit General Purpose Backup Registers 19 3 General Purpose Backup Registers GPBR User Interface Table 19 1 Register Mappin...

Page 164: ...l Purpose Backup Register x Name SYS_GPBRx Address 0xFFFFFE60 0 0xFFFFFE64 1 0xFFFFFE68 2 0xFFFFFE6C 3 Access Read write GPBR_VALUEx Value of GPBR x 31 30 29 28 27 26 25 24 GPBR_VALUEx 23 22 21 20 19...

Page 165: ...CEN OSC32EN OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register SCKCR located at address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU...

Page 166: ...32BYP bit set to 1 Disable the 32 768 Hz oscillator by setting the bit OSC32EN to 0 20 3 3 Switch from 32 768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator The same procedure must be followed...

Page 167: ...1 SAM9X25 167 11054A ATARM 27 Jul 11 SAM9X25 20 4 Slow Clock Configuration SCKC User Interface Table 20 1 Register Mapping Offset Register Name Access Reset 0x0 Slow Clock Configuration Register SCKC_...

Page 168: ...d OSC32EN 32 768 Hz Oscillator 0 32 768 Hz oscillator is disabled 1 32 768 Hz oscillator is enabled OSC32BYP 32 768Hz Oscillator Bypass 0 32 768 Hz oscillator is not bypassed 1 32 768 Hz oscillator is...

Page 169: ...lator A 3 to 20 MHz Crystal Oscillator which can be bypassed 12 MHz needed in case of USB A Fast RC Oscillator at 12 MHz A 480 MHz UTMI PLL providing a clock for the USB High Speed Device Controller A...

Page 170: ...to accept an external slow clock on XIN32 The internal 32 kHz RC oscillator and the 32 768 Hz oscillator can be enabled by setting to 1 respectively RCEN bit and OSC32EN bit in the System Controller u...

Page 171: ...e programmer must exe cute the following sequence Switch the master clock to a source different from slow clock PLL or Main Oscillator through the Power Management Controller Enable the 32 768 Hz osci...

Page 172: ...k to a source different from slow clock PLL or Main Oscillator Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1 Wait internal 32 kHz RC Startup Time for clock stabil...

Page 173: ...d OSC32EN 32768 Hz oscillator 0 32768Hz oscillator is disabled 1 32768Hz oscillator is enabled OSC32BYP 32768Hz oscillator bypass 0 32768Hz oscillator is not bypassed 1 32768Hz oscillator is bypassed...

Page 174: ...rystal oscillator or by the on chip 12 MHz RC oscillator This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected The 12 MHz crystal o...

Page 175: ...guration PLL DDR2 etc at 12 MHz instead of 32 kHz during 12 MHz oscillator start up Figure 21 5 PMC Startup On Chip 12M RC OSC Main Clock Main Clock Oscillator MOSCXTEN MOSCRCEN MOSCSEL XIN XOUT MOSCX...

Page 176: ...me procedure must be followed to switch from a 12 MHz crystal to the internal 12 MHz RC oscillator Enable the internal 12 MHz RC oscillator for low power by setting the bit MOSCRCEN to 1 Wait internal...

Page 177: ...ource of Main Clock The advantage of the 12 MHz Fast RC Oscillator is to have fast startup time this is why it is selected by default to start up the system and when entering in Wait Mode The advantag...

Page 178: ...plied to the source signal frequency is MULA 1 DIVA When MULA is written to 0 the PLLA is disabled and its power consumption is saved Re enabling the PLLA can be performed by writing a value higher th...

Page 179: ...PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0 At this time the LOCKU bit is set in...

Page 180: ...ck PCK Master Clock MCK in particular to the Matrix the memory interfaces the peripheral bridge The divider can be 2 3 or 4 Each peripheral embeds its own divider programmable in the PMC User Interfac...

Page 181: ...ck to be faster than the Master Clock The Master Clock selection is made by writing the CSS field Clock Source Selection in PMC_MCKR Master Clock Register The prescaler supports the division by a powe...

Page 182: ...Processor Clock is automatically re enabled by any enabled fast or normal interrupt or by the reset of the product Note The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operatio...

Page 183: ...Controller controls the clocks of the DDR memory It provides SysClk DDR internal clock That clock is used by the DDR Controller to provide DDR control data and DDR clock signals The DDR clock can be e...

Page 184: ...PLLACK PLLADIV2 the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES Prescaler field...

Page 185: ...he following parameters MULA DIVA is modified LOCKA bit will go low to indicate that PLLA is not ready yet When PLLA is locked LOCKA will be set again The user is constrained to wait for LOCKA bit to...

Page 186: ...C_IER register The PMC_MCKR register must not be programmed in a single write operation The pre ferred programming sequence for the PMC_MCKR register is as follows If a new value for CSS field corresp...

Page 187: ...r clock is equal to slow clock Once the PMC_PCKx register has been programmed The corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in...

Page 188: ...the UPLL Clock 2 PLLCOUNT designates either PLLACOUNT or UPLLCOUNT Table 22 1 Clock Switching Timings Worst Case From Main Clock SLCK PLL Clock To Main Clock 4 x SLCK 2 5 x Main Clock 3 x PLL Clock 4...

Page 189: ...12 2 Clock Switching Waveforms Figure 22 3 Switch Master Clock from Slow Clock to PLL Clock Figure 22 4 Switch Master Clock from Main Clock to Slow Clock Slow Clock LOCK MCKRDY Master Clock Write PMC...

Page 190: ...5 Change PLLA Programming Figure 22 6 Programmable Clock Output Programming Slow Clock Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Write CKGR_PLLAR PLL Clock PCKRDY PCKx Output Write PMC_PCKx Writ...

Page 191: ...PLLA Register CKGR_PLLAR Read write 0x0000_3F00 0x002C Reserved 0x0030 Master Clock Register PMC_MCKR Read write 0x0000_0001 0x0034 Reserved 0x0038 USB Clock Register PMC_USB Read write 0x0000_0000 0x...

Page 192: ...ck Enable 0 No effect 1 Enables the soft modem clock UHP USB Host OHCI Clocks Enable 0 No effect 1 Enables the UHP48M and UHP12M OHCI clocks UDP USB Device Clock Enable 0 No effect 1 Enables the USB D...

Page 193: ...isable 0 No effect 1 Disables the DDR clock SMDCK SMD Clock Disable 0 No effect 1 Disables the soft modem clock UHP USB Host OHCI Clock Disable 0 No effect 1 Disables the UHP48M and UHP12M OHCI clocks...

Page 194: ...t modem clock is disabled 1 The soft modem clock is enabled UHP USB Host Port Clock Status 0 The UHP48M and UHP12M OHCI clocks are disabled 1 The UHP48M and UHP12M OHCI clocks are enabled UDP USB Devi...

Page 195: ...31 refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 2 Programming the control bits of the Peripheral ID that are not implemented has no effect on the beha...

Page 196: ...isables the corresponding peripheral clock Note PID2 to PID31 refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 31 30 29 28 27 26 25 24 PID31 PID30 PID29 P...

Page 197: ...is disabled 1 The corresponding peripheral clock is enabled Note PID2 to PID31 refer to identifiers as defined in the section Peripheral Identifiers in the product datasheet 31 30 29 28 27 26 25 24 P...

Page 198: ...is set once the UTMI PLL startup time is achieved UPLLCOUNT UTMI PLL Start up Time Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start up time BIASEN UTMI BIAS Enable 0 Th...

Page 199: ...N must be set to 0 An external clock must be connected on XIN When MOSCXTBY is set the MOSCXTS flag in PMC_SR is automatically set Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag...

Page 200: ...CKGR_MCFR Address 0xFFFFFC24 Access Read only MAINF Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods MAINFRDY Main Clock Ready 0 MAINF value is not valid or the...

Page 201: ...fore the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written OUTA PLLA Clock Frequency Range To optimize clock performance this field must be programmed as specified in PLL Characteristics in the E...

Page 202: ...K Selected clock 1 CLOCK_DIV2 Selected clock divided by 2 2 CLOCK_DIV4 Selected clock divided by 4 3 CLOCK_DIV8 Selected clock divided by 8 4 CLOCK_DIV16 Selected clock divided by 16 5 CLOCK_DIV32 Sel...

Page 203: ...054A ATARM 27 Jul 11 SAM9X25 203 11054A ATARM 27 Jul 11 SAM9X25 PLLADIV2 PLLA divisor by 2 Value Name Description 0 NOT_DIV2 PLLA clock frequency is divided by 1 1 DIV2 PLLA clock frequency is divided...

Page 204: ...MC_USB Address 0xFFFFFC38 Access Read write USBS USB OHCI Input Clock Selection 0 USB Clock Input is PLLA 1 USB Clock Input is UPLL USBDIV Divider for USB OHCI Clock USB Clock is Input clock divided b...

Page 205: ...Name PMC_SMD Address 0xFFFFFC3C Access Read write SMDS SMD input clock selection 0 SMD Clock Input is PLLA 1 SMD Clock Input is UPLL SMDDIV Divider for SMD Clock SMD Clock is Input clock divided by SM...

Page 206: ...CSS Value name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLACK PLLADIV2 is selected 3 UPLL_CLK UPLL Clock is selected 4 MCK_CLK Master Clock is select...

Page 207: ...le MCKRDY Master Clock Ready Interrupt Enable LOCKU UTMI PLL Lock Interrupt Enable PCKRDYx Programmable Clock Ready x Interrupt Enable MOSCSELS Main Oscillator Selection Status Interrupt Enable MOSCRC...

Page 208: ...e MCKRDY Master Clock Ready Interrupt Disable LOCKU UTMI PLL Lock Interrupt Enable PCKRDYx Programmable Clock Ready x Interrupt Disable MOSCSELS Main Oscillator Selection Status Interrupt Disable MOSC...

Page 209: ...ock is not ready 1 UPLL Clock is ready OSCSELS Slow Clock Oscillator Selection 0 Internal slow clock RC oscillator is selected 1 External slow clock 32 kHz oscillator is selected PCKRDYx Programmable...

Page 210: ...least one clock failure detection of the main on chip RC oscillator clock has occurred since the last read of PMC_SR CFDS Clock Failure Detector Status 0 A clock failure of the main on chip RC oscill...

Page 211: ...PLLA Lock Interrupt Mask MCKRDY Master Clock Ready Interrupt Mask PCKRDYx Programmable Clock Ready x Interrupt Mask MOSCSELS Main Oscillator Selection Status Interrupt Mask MOSCRCS Main On Chip RC St...

Page 212: ...PR Address 0xFFFFFC80 Access Write only ICPLLA Charge Pump Current To optimize clock performance this field must be programmed as specified in PLL A Characteristics in the Electrical Char acteristics...

Page 213: ...er on page 192 PMC System Clock Disable Register on page 193 PMC Clock Generator Main Clock Frequency Register on page 200 PMC Clock Generator PLLA Register on page 201 PMC Master Clock Register on pa...

Page 214: ...tion has occurred since the last read of the PMC_WPSR register If this violation is an unauthor ized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC...

Page 215: ...dentifiers as defined in the section Peripheral Identifiers in the product datasheet CMD Command 0 Read mode 1 Write mode DIV Divisor Value EN Enable 0 Selected Peripheral clock is disabled 1 Selected...

Page 216: ...216 11054A ATARM 27 Jul 11 SAM9X25 216 11054A ATARM 27 Jul 11 SAM9X25...

Page 217: ...ations Multi drive capability similar to an open drain I O line Control of the pull up and pull down of the I O line Input visibility and output control The PIO Controller also features a synchronous...

Page 218: ...d Peripheral Embedded Peripheral PIO Interrupt PIO Controller Up to 32 pins PMC Up to 32 peripheral IOs Up to 32 peripheral IOs PIO Clock APB Interrupt Controller Data Enable PIN 31 PIN 1 PIN 0 Data E...

Page 219: ...RQs are used only as inputs 23 4 3 Power Management The Power Management Controller controls the PIO Controller clock in order to save power Writing any of the registers of the user interface does not...

Page 220: ...O Interrupt Up to 32 possible inputs PIO_ISR 31 PIO_IDR 31 PIO_IMR 31 PIO_IER 31 Pad PIO_PUDR 0 PIO_PUSR 0 PIO_PUER 0 PIO_MDDR 0 PIO_MDSR 0 PIO_MDER 0 PIO_CODR 0 PIO_ODSR 0 PIO_SODR 0 PIO_PDR 0 PIO_PS...

Page 221: ...one or two peripheral functions the selection is controlled with the registers PIO_PER PIO Enable Register and PIO_PDR PIO Disable Register The regis ter PIO_PSR PIO Status Register is the result of t...

Page 222: ...I O line is driven by the PIO controller The level driven on an I O line can be determined by writing in PIO_SODR Set Output Data Register and PIO_CODR Clear Output Data Register These write operatio...

Page 223: ...an input or driven by the PIO controller or driven by a peripheral Reading the I O line levels requires the clock of the PIO controller to be enabled otherwise PIO_PDSR reads the levels present on the...

Page 224: ...ing of its occurrence Thus for a pulse to be visible it must exceed 1 Selected Clock cycle whereas for a glitch to be reliably filtered out its duration must not exceed 1 2 Selected Clock cycle The fi...

Page 225: ...odes Enable Register and PIO_AIMDR Additional Interrupt Modes Disable Register The current state of this selection can be read through the PIO_AIMMR Additional Interrupt Modes Mask Register These Addi...

Page 226: ...en PIO_ISR is read must be handled When an Interrupt is enabled on a Level the interrupt is generated as long as the interrupt source is not cleared even if some read accesses in PIO_ISR are performed...

Page 227: ...h0000_004A in PIO_FELLSR Figure 23 8 Input Change Interrupt Timings if there are no Additional Interrupt Modes 23 5 11 I O Lines Lock When an I O line is controlled by a peripheral particularly the P...

Page 228: ...agation delay of the pad buffers is the inherent delay of the pad buffer When programming 0xF in fields the propagation delay of the corresponding pad is maximal Figure 23 9 Programmable I O Delays 23...

Page 229: ...gister PIO_WPMR with the appropriate access key WPKEY The protected registers are PIO Enable Register on page 234 PIO Disable Register on page 234 PIO Output Enable Register on page 235 PIO Output Dis...

Page 230: ...ge interrupt no pull up resistor no glitch filter I O lines 16 to 19 assigned to peripheral A functions with pull up resistor I O lines 20 to 23 assigned to peripheral B functions with pull down resis...

Page 231: ..._OSR Read only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enable Register PIO_IFER Write only 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write only 0x0028 Glitch Input Filter Sta...

Page 232: ...000000 0x00AC Reserved 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write only 0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write only 0x00B8 Additional Interrupt Modes...

Page 233: ...r to be enabled otherwise PIO_PDSR reads the levels present on the I O line at the time the clock was disabled 4 PIO_ISR is reset at 0x0 However the first read of the register may read a different val...

Page 234: ...04 PIOB 0xFFFFF804 PIOC 0xFFFFFA04 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 PIO Disable 0 No effect 1 Disables the...

Page 235: ...610 PIOB 0xFFFFF810 PIOC 0xFFFFFA10 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Output Enable 0 No effect 1 Enables th...

Page 236: ...ister Name PIO_OSR Address 0xFFFFF418 PIOA 0xFFFFF618 PIOB 0xFFFFF818 PIOC 0xFFFFFA18 PIOD Access Read only P0 P31 Output Status 0 The I O line is a pure input 1 The I O line is enabled in output 31 3...

Page 237: ...424 PIOA 0xFFFFF624 PIOB 0xFFFFF824 PIOC 0xFFFFFA24 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Input Filter Disable 0...

Page 238: ...PIO_SODR Address 0xFFFFF430 PIOA 0xFFFFF630 PIOB 0xFFFFF830 PIOC 0xFFFFFA30 PIOD Access Write only P0 P31 Set Output Data 0 No effect 1 Sets the data to be driven on the I O line 31 30 29 28 27 26 25...

Page 239: ...B 0xFFFFF838 PIOC 0xFFFFFA38 PIOD Access Read only or Read write P0 P31 Output Data Status 0 The data to be driven on the I O line is 0 1 The data to be driven on the I O line is 1 31 30 29 28 27 26 2...

Page 240: ...FFFF640 PIOB 0xFFFFF840 PIOC 0xFFFFFA40 PIOD Access Write only P0 P31 Input Change Interrupt Enable 0 No effect 1 Enables the Input Change Interrupt on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29...

Page 241: ...IOB 0xFFFFF848 PIOC 0xFFFFFA48 PIOD Access Read only P0 P31 Input Change Interrupt Mask 0 Input Change Interrupt is disabled on the I O line 1 Input Change Interrupt is enabled on the I O line 31 30 2...

Page 242: ...r Name PIO_MDER Address 0xFFFFF450 PIOA 0xFFFFF650 PIOB 0xFFFFF850 PIOC 0xFFFFFA50 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Registe...

Page 243: ...A 0xFFFFF658 PIOB 0xFFFFF858 PIOC 0xFFFFFA58 PIOD Access Read only P0 P31 Multi Drive Status 0 The Multi Drive is disabled on the I O line The pin is driven at high and low level 1 The Multi Drive is...

Page 244: ...4 PIOA 0xFFFFF664 PIOB 0xFFFFF864 PIOC 0xFFFFFA64 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Up Enable 0 No effe...

Page 245: ...FFF868 PIOC 0xFFFFFA68 PIOD Access Read only P0 P31 Pull Up Status 0 Pull Up resistor is enabled on the I O line 1 Pull Up resistor is disabled on the I O line 31 30 29 28 27 26 25 24 P31 P30 P29 P28...

Page 246: ...it is set to 0 in PIO_ABCDSR2 0 Assigns the I O line to the Peripheral A function 1 Assigns the I O line to the Peripheral B function If the same bit is set to 1 in PIO_ABCDSR2 0 Assigns the I O line...

Page 247: ...it is set to 0 in PIO_ABCDSR1 0 Assigns the I O line to the Peripheral A function 1 Assigns the I O line to the Peripheral C function If the same bit is set to 1 in PIO_ABCDSR1 0 Assigns the I O line...

Page 248: ...ddress 0xFFFFF484 PIOA 0xFFFFF684 PIOB 0xFFFFF884 PIOC 0xFFFFFA84 PIOD Access Write only P0 P31 Debouncing Filtering Select 0 No Effect 1 The Debouncing Filter is able to filter pulses with a duration...

Page 249: ...to filter pulses with a duration Tdiv_slclk 2 23 7 29 PIO Slow Clock Divider Debouncing Register Name PIO_SCDR Address 0xFFFFF48C PIOA 0xFFFFF68C PIOB 0xFFFFF88C PIOC 0xFFFFFA8C PIOD Access Read writ...

Page 250: ...FFFFF494 PIOA 0xFFFFF694 PIOB 0xFFFFF894 PIOC 0xFFFFFA94 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Down Enable...

Page 251: ...is register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Pull Down Status 0 Pull Down resistor is enabled on the I O line 1 Pull Down resistor is disabled o...

Page 252: ...F4A4 PIOA 0xFFFFF6A4 PIOB 0xFFFFF8A4 PIOC 0xFFFFFAA4 PIOD Access Write only This register can only be written if the WPEN bit is cleared in PIO Write Protect Mode Register P0 P31 Output Write Disable...

Page 253: ...FFF4B0 PIOA 0xFFFFF6B0 PIOB 0xFFFFF8B0 PIOC 0xFFFFFAB0 PIOD Access Write only P0 P31 Additional Interrupt Modes Enable 0 No effect 1 The interrupt source is the event described in PIO_ELSR and PIO_FRL...

Page 254: ...FFF4B8 PIOA 0xFFFFF6B8 PIOB 0xFFFFF8B8 PIOC 0xFFFFFAB8 PIOD Access Read only P0 P31 Peripheral CD Status 0 The interrupt source is a Both Edge detection event 1 The interrupt source is described by th...

Page 255: ...0xFFFFF6C4 PIOB 0xFFFFF8C4 PIOC 0xFFFFFAC4 PIOD Access Write only P0 P31 Level Interrupt Selection 0 No effect 1 The interrupt source is a Level detection event 31 30 29 28 27 26 25 24 P31 P30 P29 P2...

Page 256: ...A 0xFFFFF6D0 PIOB 0xFFFFF8D0 PIOC 0xFFFFFAD0 PIOD Access Write only P0 P31 Falling Edge Low Level Interrupt Selection 0 No effect 1 The interrupt source is set to a Falling Edge detection or Low Level...

Page 257: ...D8 PIOC 0xFFFFFAD8 PIOD Access Read only P0 P31 Edge Level Interrupt Source Selection 0 The interrupt source is a Falling Edge detection if PIO_ELSR 0 or Low Level detection event if PIO_ELSR 1 1 The...

Page 258: ...0xFFFFF6E0 PIOB 0xFFFFF8E0 PIOC 0xFFFFFAE0 PIOD Access Read only P0 P31 Lock Status 0 The I O line is not locked 1 The I O line is locked 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22...

Page 259: ...n page 234 PIO Disable Register on page 234 PIO Output Enable Register on page 235 PIO Output Disable Register on page 236 PIO Input Filter Enable Register on page 237 PIO Input Filter Disable Registe...

Page 260: ...ul 11 SAM9X25 260 11054A ATARM 27 Jul 11 SAM9X25 WPKEY Write Protect KEY Should be written at value 0x50494F PIO in ASCII Writing any other value in this field aborts the write operation of the WPEN b...

Page 261: ...1 A Write Protect Violation has occurred since the last read of the PIO_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported i...

Page 262: ...Schmitt Trigger is enabled 1 Schmitt Trigger is disabled 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHM...

Page 263: ...s 0xFFFFF510 PIOA 0xFFFFF710 PIOB 0xFFFFF910 PIOC 0xFFFFFB10 PIOD Access Read write Reset See Figure 23 2 Delay x Gives the number of elements in the delay line associated to pad x 31 30 29 28 27 26 2...

Page 264: ...PIOC 0xFFFFFB14 PIOD Access Read write Reset 0x0 LINEx x 0 15 Drive of PIO line x 31 30 29 28 27 26 25 24 LINE15 LINE14 LINE13 LINE12 23 22 21 20 19 18 17 16 LINE11 LINE10 LINE9 LINE8 15 14 13 12 11 1...

Page 265: ...0xFFFFFB18 PIOD Access Read write Reset 0x0 LINEx x 16 31 Drive of PIO line x 31 30 29 28 27 26 25 24 LINE31 LINE30 LINE29 LINE28 23 22 21 20 19 18 17 16 LINE27 LINE26 LINE25 LINE24 15 14 13 12 11 10...

Page 266: ...266 11054A ATARM 27 Jul 11 SAM9X25 266 11054A ATARM 27 Jul 11 SAM9X25...

Page 267: ...cessor making possible the handling of the DCC under interrupt control Chip Identifier registers permit recognition of the device and its revision These registers inform as to the sizes and types of t...

Page 268: ...Transmit Receive Chip ID Interrupt Control Peripheral Bridge Parallel Input Output DTXD DRXD Power Management Controller ARM Processor force_ntrst COMMRX COMMTX MCK nTRST Power on Reset dbgu_irq APB D...

Page 269: ...terrupt lines and other system peripheral interrupts as shown in Figure 24 1 This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered 24 5 UART Oper...

Page 270: ...24 5 2 2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations and this affects only its receiver The Debug Unit receiver detects the start of a received character by...

Page 271: ...new character is received the OVRE status bit in DBGU_SR is set OVRE is cleared when the software writes the control reg ister DBGU_CR with the bit RSTSTA Reset Status at 1 Figure 24 7 Receiver Overru...

Page 272: ...om this command the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission The programmer can disable the transmitter by wr...

Page 273: ...As soon as the first character is completed the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again showing that the holding register is empty When both the...

Page 274: ...as in idle state The Remote Loopback mode directly connects the DRXD pin to the DTXD line The transmitter and the receiver are disabled and have no effect This mode allows a bit by bit retransmission...

Page 275: ...isters contain a hard wired value that is read only The first register contains the following fields EXT shows the use of the extension identifier register NVPTYP and NVPSIZ identifies the type of emb...

Page 276: ...00C Interrupt Disable Register DBGU_IDR Write only 0x0010 Interrupt Mask Register DBGU_IMR Read only 0x0 0x0014 Status Register DBGU_SR Read only 0x0018 Receive Holding Register DBGU_RHR Read only 0x0...

Page 277: ...XDIS Receiver Disable 0 No effect 1 The receiver is disabled If a character is being processed and RSTRX is not set the character is completed before the receiver is stopped TXEN Transmitter Enable 0...

Page 278: ...e 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE PAR 7 6 5 4 3 2 1 0 Value Name Description 0b000 EVEN Even Parity 0b001 ODD Odd Parity 0b010 SPACE Space Parity forced to...

Page 279: ...terrupt OVRE Enable Overrun Error Interrupt FRAME Enable Framing Error Interrupt PARE Enable Parity Error Interrupt TXEMPTY Enable TXEMPTY Interrupt COMMTX Enable COMMTX from ARM Interrupt COMMRX Enab...

Page 280: ...rrupt OVRE Disable Overrun Error Interrupt FRAME Disable Framing Error Interrupt PARE Disable Parity Error Interrupt TXEMPTY Disable TXEMPTY Interrupt COMMTX Disable COMMTX from ARM Interrupt COMMRX D...

Page 281: ...rupt OVRE Mask Overrun Error Interrupt FRAME Mask Framing Error Interrupt PARE Mask Parity Error Interrupt TXEMPTY Mask TXEMPTY Interrupt COMMTX Mask COMMTX Interrupt COMMRX Mask COMMRX Interrupt 0 Th...

Page 282: ...RSTSTA FRAME Framing Error 0 No framing error has occurred since the last RSTSTA 1 At least one framing error has occurred since the last RSTSTA PARE Parity Error 0 No parity error has occurred since...

Page 283: ...r if RXRDY is set 24 6 8 Debug Unit Transmit Holding Register Name DBGU_THR Address 0xFFFFF21C Access Write only TXCHR Character to be Transmitted Next character to be transmitted after the current ch...

Page 284: ...bug Unit Baud Rate Generator Register Name DBGU_BRGR Address 0xFFFFF220 Access Read write CD Clock Divisor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 7 6 5 4 3 2 1 0 CD V...

Page 285: ...31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 7 6 5 4 3 2 1 0 EPROC VERSION Value Name Description 1 ARM946ES ARM946ES 2 ARM7TDMI AR...

Page 286: ...tes 3 32K 32K bytes 4 Reserved 5 64K 64K bytes 6 Reserved 7 128K 128K bytes 8 Reserved 9 256K 256K bytes 10 512K 512K bytes 11 Reserved 12 1024K 1024K bytes 13 Reserved 14 2048K 2048K bytes 15 Reserve...

Page 287: ...SAM7SExx AT91SAM7SExx Series 0x73 AT91SAM7Lxx AT91SAM7Lxx Series 0x75 AT91SAM7Xxx AT91SAM7Xxx Series 0x76 AT91SAM7SLxx AT91SAM7SLxx Series 0x80 ATSAM3UxC ATSAM3UxC Series 100 pin version 0x81 ATSAM3Ux...

Page 288: ...extended Chip ID exists 0x99 ATSAM3SDxB ATSAM3SDxB Series 64 pin version 0x9A ATSAM3SDxC ATSAM3SDxC Series 100 pin version 0xA5 Reserved 0xF0 AT75Cxx AT75Cxx Series Value Name Description 0 ROM ROM 1...

Page 289: ...5 24 6 11 Debug Unit Chip ID Extension Register Name DBGU_EXID Address 0xFFFFF244 Access Read only EXID Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0 31 30 29 28 27 26 25 24 EXID 23 22 21...

Page 290: ...r Name DBGU_FNR Address 0xFFFFF248 Access Read write FNTRST Force NTRST 0 NTRST of the ARM processor s TAP controller is driven by the power_on_reset signal 1 NTRST of the ARM processor s TAP controll...

Page 291: ...rix to support application specific features 25 2 Embedded Characteristics 12 layer Matrix handling requests from 11 masters Programmable Arbitration strategy Fixed priority Arbitration Round Robin Ar...

Page 292: ...llowing a different arbi tration per slave to be programmed Table 25 1 List of Bus Matrix Masters Master 0 ARM926 Instruction Master 1 ARM926 Data Master 2 3 DMA Controller 0 Master 4 5 DMA Controller...

Page 293: ...lowing table Table 25 3 Master to Slave Access Masters 0 1 2 3 4 5 6 7 8 9 10 11 Slaves ARM926 Instr ARM926 Data DMA 0 DMA 1 USB DeviceHS DMA USB Host HS EHCI USB Host HS OHCI Reserved EMAC 0 DMA EMAC...

Page 294: ...face provides the Slave Configuration Registers one for every slave that set a default master for each slave The Slave Configuration Register contains two fields DEFMSTR_TYPE and FIXED_DEFMSTR The 2 b...

Page 295: ...he user with the possibility of choosing between 2 arbitration types or mixing them for each slave 1 Round robin Arbitration default 2 Fixed Priority Arbitration The resulting algorithm may be complem...

Page 296: ...g that the AHB specification natively limits all word bursts to 256 beats and double word bursts to 128 beats because of its 1 Kilobyte address boundaries Unless duly needed the ULBT should be left at...

Page 297: ...value the higher the master priority All combinations of MxPR values are allowed for all masters and slaves For example some masters might be assigned to the highest priority pool round robin and the...

Page 298: ...in the MATRIX Write Protect Mode Register MATRIX_WPMR If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected then the WPVS flag in the MATRIX Write Pr...

Page 299: ...Configuration Register 3 MATRIX_SCFG3 Read write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read write 0x000001FF 0x0054 Slave Configuration Register 5 MATRIX_SCFG5 Read write 0x000...

Page 300: ...0x00000000 0x00C4 Priority Register B for Slave 8 MATRIX_PRBS8 Read write 0x00000000 0x00C8 Priority Register A for Slave 9 MATRIX_PRAS9 Read write 0x00000000 0x00CC Priority Register B for Slave 9 MA...

Page 301: ...ngle accesses allowing re arbitration at each beat of the INCR burst 2 4 beat Burst The undefined length burst is split into 4 beat bursts allowing re arbitration at each 4 beat burst end 3 8 beat Bur...

Page 302: ...e In most cases this feature is not needed and should be disabled for power saving See Section 25 5 1 2 on page 296 DEFMSTR_TYPE Default Master Type 0 No Default Master At the end of the current slave...

Page 303: ...ter x for accessing the selected slave The higher the number the higher the priority All the masters programmed with the same MxPR value for the slave make up a priority pool Round robin arbitration i...

Page 304: ...ority of Master x for accessing the selected slave The higher the number the higher the priority All the masters programmed with the same MxPR value for the slave make up a priority pool Round robin a...

Page 305: ...0 Access Read write RCBx Remap Command Bit for Master x 0 Disable remapped address decoding for the selected Master 1 Enable remapped address decoding for the selected Master 31 30 29 28 27 26 25 24 2...

Page 306: ...Chip Configuration User Interface Table 25 5 Chip Configuration User Interface Offset Register Name Access Reset Value 0x0110 0x011C Reserved 0x0120 EBI Chip Select Assignment Register CCFG_EBICSA Rea...

Page 307: ...ata Bus Pull Down Configuration 0 EBI D0 D15 Data Bus bits are internally pulled down to the ground 1 EBI D0 D15 Data Bus bits are not internally pulled down EBI_DRIVE EBI I O Drive Configuration This...

Page 308: ...DDR Multi port is enabled performance is increased Warning Use only with NFDO0_ON_D16 0 The system behavior is unpredictable if ND0_ON_D16 is set to 1 at the same time Note EBI Chip Select 1 is to be...

Page 309: ...corresponds to 0x4D4154 MAT in ASCII 1 Enables the Write Protect if WPKEY corresponds to 0x4D4154 MAT in ASCII Protects the entire MATRIX address space from address offset 0x000 to 0x1FC WPKEY Write P...

Page 310: ...No Write Protect Violation has occurred since the last write of the MATRIX_WPMR 1 At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR WPVSRC Write Protect Violat...

Page 311: ...d circuitry that greatly reduces the requirements for external components Furthermore the EBI handles data transfers with up to six external devices each assigned to six address spaces defined by the...

Page 312: ...r Interface Chip Select Assignor Static Memory Controller DDR2 LPDDR SDRAM Controller Bus Matrix APB AHB Address Decoders A16 BA0 A0 NBS0 A1 NWR2 NBS2 DQM2 A17 BA1 NCS0 NRD NCS1 SDCS NWR0 NWE NWR1 NBS...

Page 313: ...ND Flash Support EBI_NANDCS NAND Flash Chip Select Line Output Low EBI_NANDOE NAND Flash Output Enable Output Low EBI_NANDWE NAND Flash Write Enable Output Low DDR2 SDRAM Controller EBI_SDCK EBI_SDCK...

Page 314: ...and External Static Device Connections Signals EBI_ Pins of the Interfaced Device 8 bit Static Device 2 x 8 bit Static Devices 16 bit Static Device 4 x 8 bit Static Devices 2 x 16 bit Static Devices...

Page 315: ...DQM1 DQM0 DQM1 DQS0 DQS1 VDDIOM DQS0 DQS1 A2 A10 VDDIOM A 0 8 A 0 8 A11 VDDIOM A9 A9 SDA10 VDDIOM A10 A10 A12 VDDIOM A13 A14 VDDIOM A 11 12 A 11 12 A15 VDDIOM A13 A16 BA0 VDDIOM BA0 BA0 A17 BA1 VDDIOM...

Page 316: ...ultiplex controller circuit that shares the pins between the different Memory Controllers programmable NAND Flash support logic 26 5 3 1 Bus Multiplexing The EBI offers a complete set of control signa...

Page 317: ...rol of these delays is as follows EBI DDR2SDRC SMC NAND Flash D 15 0 controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface D 0 DELAY1 3 0 D 1 DELAY1 7 4 D 6 DELAY1 27 24 D 7 DE...

Page 318: ...NAND Flash independently of SDRAM power supply A switch NFD0_ON_D16 enables the user to select NAND Flash path on D0 D15 or D16 D32 depending on memory power supplies This switch is located in the reg...

Page 319: ...Controller The product embeds a multi port DDR2SDR Controller This allows to use three additional ports on DDR2SDRC to lessen the EBI load from a part of DDR2 or LP DDR accesses This increases the ba...

Page 320: ...space reserved to NCS3 i e between 0x4000 0000 and 0x4FFF FFFF The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active...

Page 321: ...mple 26 5 4 Implementation Examples The following hardware configurations are given for illustration only The user should refer to the memory manufacturer web site to check current device availability...

Page 322: ...the EBI Chip Select Register located in the bus matrix memory space Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency The DDR2 initialization sequence is described i...

Page 323: ...EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space Initialize the DDR2 Controller depending on the LP DDR device and system bus frequency The LP DDR initialization sequen...

Page 324: ...I Chip Select Assignment Register located in the bus matrix memory space Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency The Data Bus Width is to be programmed t...

Page 325: ...D7 A2 SDA10 D8 D1 A4 D13 D11 A7 SDCS BA0 BA1 CLK CKE CAS RAS WE A 1 14 D 0 31 VDDIOM VDDIOM VDDIOM VDDIOM 256 Mbits 256 Mbits SDRAM C13 100NF C13 100NF C1 100NF C1 100NF C11 100NF C11 100NF R4 0R R4 0...

Page 326: ...A22 during accesses Configure a PIO line as an input to manage the Ready Busy signal Configure Static Memory Controller CS3 Setup Pulse Cycle and Mode accordingly to NAND Flash timings the data bus wi...

Page 327: ...D8 D11 D12 D10 D9 D13 D15 NANDOE NANDWE ANY PIO ALE CLE D 0 15 ANY PIO 3V3 3V3 2 Gb TSOP48 PACKAGE R1 10K R1 10K R2 10K R2 10K C2 100NF C2 100NF C1 100NF C1 100NF U1 MT29F2G16AABWP ET U1 MT29F2G16AABW...

Page 328: ...rix memory space Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register Reserve A21 A22 for ALE CLE functions Address and Command Latches are contr...

Page 329: ...volatile memory at slow clock For another configuration configure the Static Memory Controller CS0 Setup Pulse Cycle and Mode depending on Flash timings and system bus frequency A21 A22 A1 A2 A3 A4 A...

Page 330: ...330 11054A ATARM 27 Jul 11 SAM9X25 330 11054A ATARM 27 Jul 11 SAM9X25...

Page 331: ...oefficients These coefficients belong to GF 2 13 or GF 2 14 The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial 27 2 Embedded Characteristics Pr...

Page 332: ...lid range When the PMEERRLOC engine is searching for roots the BUSY field of the ELSR remains asserted An interrupt is asserted at the end of the computation and the DONE bit of the ELSIR register is...

Page 333: ...Error Location Status Register PMERRLOC_ELSR Read write 0x00000000 0x014 Error Location Interrupt Enable register PMERRLOC_ELIER Read only 0x00000000 0x018 Error Location Interrupt Disable Register PM...

Page 334: ...PMERRLOC_ELCFG Address 0xFFFFE600 Access Read write Reset 0x00000000 ERRNUM Number of Errors SECTORSZ Sector Size 0 The ECC computation is based on a 512 byte sector 1 The ECC computation is based on...

Page 335: ...11 SAM9X25 27 5 2 Error Location Primitive Register Name PMERRLOC_ELPRIM Address 0xFFFFE604 Access Read only Reset 0x00000000 PRIMITIV Primitive Polynomial 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 336: ...AM9X25 27 5 3 Error Location Enable Register Name PMERRLOC_ELEN Address 0xFFFFE608 Access Read write Reset 0x00000000 ENINIT Initial Number of Bits in the Codeword 31 30 29 28 27 26 25 24 23 22 21 20...

Page 337: ...7 Jul 11 SAM9X25 27 5 4 Error Location Disable Register Name PMERRLOC_ELDIS Address 0xFFFFE60C Access Read write Reset 0x00000000 DIS Disable Error Location Engine 31 30 29 28 27 26 25 24 23 22 21 20...

Page 338: ...27 Jul 11 SAM9X25 27 5 5 Error Location Status Register Name PMERRLOC_ELSR Address 0xFFFFE610 Access Read write Reset 0x00000000 BUSY Error Location Engine Busy 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 339: ...AM9X25 27 5 6 Error Location Interrupt Enable Register Name PMERRLOC_ELIER Address 0xFFFFE614 Access Read only Reset 0x00000000 DONE Computation Terminated Interrupt Enable 31 30 29 28 27 26 25 24 23...

Page 340: ...M9X25 27 5 7 Error Location Interrupt Disable Register Name PMERRLOC_ELIDR Address 0xFFFFE618 Access Read only Reset 0x00000000 DONE Computation Terminated Interrupt Disable 31 30 29 28 27 26 25 24 23...

Page 341: ...SAM9X25 27 5 8 Error Location Interrupt Mask Register Name PMERRLOC_ELIMR Address 0xFFFFE61C Access Read only Reset 0x00000000 DONE Computation Terminated Interrupt Mask 31 30 29 28 27 26 25 24 23 22...

Page 342: ...r Location Interrupt Status Register Name PMERRLOC_ELISR Address 0xFFFFE620 Access Read only Reset 0x00000000 DONE Computation Terminated Interrupt Status ERR_CNT Error Counter value 31 30 29 28 27 26...

Page 343: ...ccess Read Write Reset 0x00000000 SIGMAx Coefficient of degree x in the SIGMA polynomial SIGMAx belongs to the finite field GF 2 13 when the sector size is set to 512 bytes SIGMAx belongs to the finit...

Page 344: ...to 512 bytes the ERRLOCN points to 4096 when the last bit of the sector area is corrupted If the sector size is set to 1024 bytes the ERRLOCN points to 8192 when the last bit of the sector area is co...

Page 345: ...ector of data 28 2 Embedded Characteristics Multibit Error Correcting Code Algorithm based on binary shortened Bose Chaudhuri and Hocquenghem BCH codes Programmable Error Correcting Capability 2 4 8 1...

Page 346: ...ATARM 27 Jul 11 SAM9X25 28 3 Block Diagram Figure 28 1 Block Diagram User Interface Programmable BCH Algorithm Static Memory Controller APB MLC SLC NAND Flash device PMECC Controller 8 Bit Data Bus C...

Page 347: ...hmetic must be available to perform addition multiplication and inversion The finite field arithmetic operations can be performed through the use of a memory mapped lookup table or direct soft ware im...

Page 348: ...re PMECC error correction capability sector size page size NAND write field set to false spare area desired layout Move the NAND Page from external Memory whether using DMA or Processor PMECC computes...

Page 349: ...DATA field of the PMECC_CTRL register When the encoding process is over the redundancy is written to the spare area in user mode USER field of the PMECC_CTRL must be set to one Table 28 1 Relevant Re...

Page 350: ...mode is entered by writing one to the DATA field of the PMECC_CTRL register Figure 28 4 NAND Write Operation Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 Spare pagesize n sectorsize sparesize...

Page 351: ...s mode is entered by writing one in the DATA field of the PMECC_CTRL register Table 28 3 Relevant Remainders Registers BCH_ERR field Sector size set to 512 bytes Sector size set to 1024 bytes 0 PMECC_...

Page 352: ...ECC This mode is entered writing one in the USER field of the PMECC_CTRL register Figure 28 7 User Read Mode Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 Spare pagesize n sectorsize sparesize...

Page 353: ...the error correcting capability NB_ERROR defines the error correcting capability selected at encoding decoding time NB_FIELD_ELEMENTS defines the number of elements in the field si is a table that ho...

Page 354: ...t encoding decoding time NB_FIELD_ELEMENTS defines the number of elements in the field int get_sigma int i int j int k mu int mu NB_ERROR_MAX 2 sigma ro int sro 2 NB_ERROR_MAX 1 discrepancy int dmu NB...

Page 355: ...i NB_ERROR i mu i 1 i 1 Compute Sigma Mu 1 And L mu check if discrepancy is set to 0 if dmu i 0 copy polynom for j 0 j 2 NB_ERROR_MAX 1 j smu i 1 j smu i j copy previous polynom order to the next lmu...

Page 356: ...inverse sro k gf_antilog gf_log dmu i NB_FIELD_ELEMENTS gf_log dmu ro gf_log sro k NB_FIELD_ELEMENTS multiply by dmu dmu ro 1 for k 0 k 2 NB_ERROR_MAX 1 k smu i 1 k smu i k sro k if smu i 1 k find the...

Page 357: ...nd the Error Position The output of the get_sigma procedure is a polynomial stored in the smu NB_ERROR 1 table The error position is the roots of that polynomial The degree of this polynomial is very...

Page 358: ...00 0x040 sec_num 0x40 0x0C PMECC ECC 3 Register PMECC_ECC3 Read only 0x00000000 0x040 sec_num 0x40 0x10 PMECC ECC 4 Register PMECC_ECC4 Read only 0x00000000 0x040 sec_num 0x40 0x14 PMECC ECC 5 Registe...

Page 359: ...c_num 0x40 0x28 PMECC REM 10 Register PMECC_REM10 Read only 0x00000000 0x240 sec_num 0x40 0x2C PMECC REM 11 Register PMECC_REM11 Read only 0x00000000 0x440 0x5FC Reserved Table 28 4 Register Mapping C...

Page 360: ...0 the spare area is skipped 1 the spare area is protected with the last sector of data for NAND read access 0 the spare area is skipped 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AUTO SPAREEN 15...

Page 361: ...spare enable is activated 0 Indicates that the spare area is not protected In that case the ECC computation takes into account the ECC area located in the spare area within the start address and the...

Page 362: ...Register Name PMECC_SAREA Address 0xFFFFE004 Access Read write Reset 0x00000000 SPARESIZE Spare Area Size The spare area size is equal to SPARESIZE 1 bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 363: ...Access Read write Reset 0x00000000 STARTADDR ECC Area Start Address byte oriented address This field indicates the first byte address of the ECC area Location 0 matches the first byte of the spare are...

Page 364: ...ECC_EADDR Address 0xFFFFE00C Access Read write Reset 0x00000000 ENDADDR ECC Area End Address byte oriented address This field indicates the last byte address of the ECC area 31 30 29 28 27 26 25 24 23...

Page 365: ...L Clock Control Register The PMECC Module data path Setup Time is set to CLKCTRL 1 This field indicates the database setup times in number of clock cycles At 133 Mhz this field must be programmed with...

Page 366: ...ontroller configuration registers remain unaffected DATA Start a Data Phase USER Start a User Mode Phase ENABLE PMECC Module Enable PMECC module must always be configured before being activated DISABL...

Page 367: ...Reset 0x00000000 BUSY The Kernel of the PMECC is Busy ENABLE PMECC Module Status 0 the PMECC Module is disabled and can be configured 1 the PMECC Module is enabled and the configuration registers can...

Page 368: ...25 28 6 8 PMECC Interrupt Enable Register Name PMECC_IER Address 0xFFFFE01C Access Write only Reset 0x00000000 ERRIE Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 369: ...9X25 28 6 9 PMECC Interrupt Disable Register Name PMECC_IDR Address 0xFFFFE020 Access Write Reset 0x00000000 ERRID Error Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 370: ...X25 28 6 10 PMECC Interrupt Mask Register Name PMECC_IMR Address 0xFFFFE024 Access Read only Reset 0x00000000 ERRIM Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 371: ...ECC_ISR Address 0xFFFFE028 Access Read only Reset 0x00000000 ERRIS Error Interrupt Status Register When set to one bit i of the PMECCISR register indicates that sector i is corrupted 31 30 29 28 27 26...

Page 372: ...FFFE100 0 3 0xFFFFE128 10 3 0xFFFFE140 0 4 0xFFFFE168 10 4 0xFFFFE180 0 5 0xFFFFE1A8 10 5 0xFFFFE1C0 0 6 0xFFFFE1E8 10 6 0xFFFFE200 0 7 0xFFFFE228 10 7 Access Read only Reset 0x00000000 ECC BCH Redund...

Page 373: ...00000 REM2NP1 BCH Remainder 2 N 1 When sector size is set to 512 bytes bit REM2NP1 13 is not used and read as zero If bit i of the REM2NP1 field is set to one then the coefficient of the X i is set to...

Page 374: ...374 11054A ATARM 27 Jul 11 SAM9X25...

Page 375: ...rrent access The SMC is provided with an automatic slow clock mode In slow clock mode it switches from user programmed waveforms to slow rate specific waveforms on read and write signals The SMC suppo...

Page 376: ...e 3 Byte 3 Select Signal Output Low A 25 2 Address Bus Output D 31 0 Data Bus I O NWAIT External Wait Signal Input Low Table 29 2 Static Memory Controller SMC Multiplexed Signals Multiplexed Signals R...

Page 377: ...ssign the Static Memory Con troller pins to their peripheral function If I O Lines of the SMC are not used by the application they can be used for other purposes by the PIO Controller Static Memory Co...

Page 378: ...of 8 16 or 32 bits can be selected for each chip select This option is con trolled by the field DBW in SMC_MODE Mode Register for the corresponding chip select Figure 29 3 shows how to connect a 512K...

Page 379: ...ta Bus SMC A0 NWE NRD NCS 2 A0 Write Enable Output Enable Memory Enable D 7 0 D 7 0 A 18 2 A 18 2 A1 A1 SMC NBS0 NWE NRD NCS 2 Low Byte Enable Write Enable Output Enable Memory Enable NBS1 High Byte E...

Page 380: ...D is provided Byte Write Access is used to connect 4 x 8 bit devices as a 32 bit memory Byte Write option is illustrated on Figure 29 6 29 8 2 2 Byte Select Access In this mode read write operations c...

Page 381: ...ignals at the SMC interface are multiplexed Table 29 3 shows signal multiplexing depending on the data bus width and the byte access type For 32 bit devices bits A0 and A1 are unused For 16 bit device...

Page 382: ...D 31 16 A 23 0 Low Byte Enable High Byte Enable Low Byte Enable High Byte Enable NBS1 NBS2 NBS3 Table 29 3 SMC Multiplexed Signal Translation Signal Name 32 bit Bus 16 bit Bus 8 bit Bus Device Type 1x...

Page 383: ...ead cycle is shown on Figure 29 8 The read cycle starts with the address setting on the memory address bus i e A 25 2 A1 A0 for 8 bit devices A 25 2 A1 for 16 bit devices A 25 2 for 32 bit devices Fig...

Page 384: ...address is set on the address bus to the point where address may change The total read cycle time is equal to NRD_CYCLE NRD_SETUP NRD_PULSE NRD_HOLD NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD All NRD and N...

Page 385: ...g chip select indicates which signal of NRD and NCS controls the read operation 29 9 2 1 Read is Controlled by NRD READ_MODE 1 Figure 29 10 shows the waveforms of a read operation of a typical asynchr...

Page 386: ...emains valid until the rising edge of NCS Data must be sampled when NCS is raised In that case the READ_MODE must be set to 0 read is controlled by NCS the SMC internally samples the data on the risin...

Page 387: ...WE hold time is defined as the hold time of address and data after the NWE rising edge The NWE waveforms apply to all byte write lines in Byte Write access mode NWR0 to NWR3 29 9 3 2 NCS Waveforms The...

Page 388: ...hold time and NCS write hold times as NWE_HOLD NWE_CYCLE NWE_SETUP NWE_PULSE NCS_WR_HOLD NWE_CYCLE NCS_WR_SETUP NCS_WR_PULSE 29 9 3 4 Null Delay Setup and Hold If null setup parameters are programmed...

Page 389: ...ernal data buffers are turned out after the NWE_SETUP time and until the end of the write cycle regardless of the programmed waveform on NCS Figure 29 14 WRITE_MODE 1 The write operation is controlled...

Page 390: ...er reading the SMC Write Protect Status Register SMC_WPSR List of the write protected registers Section 29 16 1 SMC Setup Register Section 29 16 2 SMC Pulse Register Section 29 16 3 SMC Cycle Register...

Page 391: ...ly Read Wait State on page 392 For read and write operations a null value for pulse parameters is forbidden and may lead to unpredictable behavior In read and write cycles the setup and hold time para...

Page 392: ...alid if the write controlling signal has no hold time and the read controlling signal has no setup time Figure 29 17 in NCS write controlled mode WRITE_MODE 0 if there is no hold timing on the NCS sig...

Page 393: ...18 Early Read Wait State NCS Controlled Write with No Hold Followed by a Read with No NCS Setup write cycle Early Read wait state MCK NRD NWE read cycle no setup no hold D 31 0 NBS0 NBS1 NBS2 NBS3 A0...

Page 394: ...hand if accesses before and after writing the user interface are made to the same device a Reload Configuration Wait State is inserted even if the change does not concern the current Chip Select 29 1...

Page 395: ...rnal memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select The value of TDF_CYCLES indicates the number of data float wait cycles between 0 and...

Page 396: ...ntrolled Read Access TDF 2 Figure 29 21 TDF Period in NCS Controlled Read Operation TDF 3 NBS0 NBS1 NBS2 NBS3 A0 A1 NCS NRD controlled read operation tpacc MCK NRD D 31 0 TDF 2 clock cycles A 25 2 NCS...

Page 397: ...are inserted if the TDF period is over when the next access begins 29 11 3 TDF Optimization Disabled TDF_MODE 0 When optimization is disabled tdf wait states are inserted at the end of the read transf...

Page 398: ...6 TDF_MODE 0 optimization disabled A 25 2 read1 cycle Chip Select Wait State MCK read1 controlling signal NRD read2 controlling signal NRD D 31 0 read1 hold 1 read 2 cycle read2 setup 1 5 TDF WAIT STA...

Page 399: ...rresponding chip select 29 12 1 Restriction When one of the EXNW_MODE is enabled it is mandatory to program at least one hold cycle for the read write controlling signal For that reason the NWAIT sign...

Page 400: ...g the access from the point where it was stopped See Figure 29 26 This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC The assertion of t...

Page 401: ...sertion in Frozen Mode EXNW_MODE 10 EXNW_MODE 10 Frozen READ_MODE 0 NCS_controlled NRD_PULSE 2 NRD_HOLD 6 NCS_RD_PULSE 5 NCS_RD_HOLD 3 A 25 2 MCK NCS NRD 1 0 4 3 4 3 2 5 5 5 2 2 0 2 1 0 2 1 0 1 Read c...

Page 402: ...of the access is performed This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation If the NWAIT signal...

Page 403: ...n Read Access Ready Mode EXNW_MODE 11 EXNW_MODE 11 Ready mode READ_MODE 0 NCS_controlled NRD_PULSE 7 NCS_RD_PULSE 7 A 25 2 MCK NCS NRD 4 5 6 3 2 0 0 0 1 4 5 6 3 2 1 1 Read cycle Assertion is ignored N...

Page 404: ...he hold state of the access without detecting the NWAIT signal assertion This is true in frozen mode as well as in ready mode This is illustrated on Fig ure 29 30 When EXNW_MODE is enabled ready or fr...

Page 405: ...When activated the slow mode is active on all chip selects 29 13 1 Slow Clock Mode Waveforms Figure 29 31 illustrates the read and write operations in slow clock mode They are valid on all chip selec...

Page 406: ...to support such timings Figure 29 33 illustrates the recommended procedure to properly switch from one mode to the other Figure 29 32 Clock Rate Transition Occurs while the SMC is Performing a Write O...

Page 407: ...commended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode A 25 2 NCS 1 MCK NWE 1 1 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 2 3 2 N...

Page 408: ...tsa as shown in Figure 29 34 When in page mode the SMC enables the user to define different read timings for the first access within one page and next accesses within the page Notes 1 A denotes the a...

Page 409: ...sequential Accesses If the chip select and the MSB of addresses as defined in Table 29 6 are identical then the cur rent access lies in the same page as the previous one and no page break occurs Usin...

Page 410: ...27 Jul 11 SAM9X25 410 11054A ATARM 27 Jul 11 SAM9X25 Figure 29 35 Access to Non sequential Data within the Same Page A 25 3 A 2 A1 A0 NCS MCK NRD Page address A1 A3 A7 D 7 0 NCS_RD_PULSE NRD_PULSE NR...

Page 411: ...ming 0x0 in fields Delay1 to Delay 8 no delay is added reset value and the propagation delay of the pad buffers is the inherent delay of the pad buffer When programming 0xF in field Delay1 the propaga...

Page 412: ...010101 0x10 x CS_number 0x04 SMC Pulse Register SMC_PULSE Read write 0x01010101 0x10 x CS_number 0x08 SMC Cycle Register SMC_CYCLE Read write 0x00030003 0x10 x CS_number 0x0C SMC Mode Register SMC_MOD...

Page 413: ...WRITE Access In write access the NCS signal setup length is defined as NCS setup length 128 NCS_WR_SETUP 5 NCS_WR_SETUP 4 0 clock cycles NRD_SETUP NRD Setup Length The NRD signal setup length is defin...

Page 414: ...1 clock cycle NRD_PULSE NRD Pulse Length In standard read access the NRD signal pulse length is defined in clock cycles as NRD pulse length 256 NRD_PULSE 6 NRD_PULSE 5 0 clock cycles The NRD pulse len...

Page 415: ...he sum of the setup pulse and hold steps of the NWE and NCS signals It is defined as Write cycle length NWE_CYCLE 8 7 256 NWE_CYCLE 6 0 clock cycles NRD_CYCLE Total Read Cycle Length The total read cy...

Page 416: ...ODE 1 TDF wait states will be inserted after the setup of NWE 0 The write operation is controlled by the NCS signal If TDF optimization is enabled TDF_MODE 1 TDF wait states will be inserted after the...

Page 417: ...integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal The SMC always provide one full cycle of bus turnaround after t...

Page 418: ...0 1 0xFFFFEAC4 2 0xFFFFEAC8 3 0xFFFFEACC 4 0xFFFFEAD0 5 0xFFFFEAD4 6 0xFFFFEAD8 7 0xFFFFEADC 8 Access Read write Reset Value See Table 29 8 Delay x Gives the number of elements in the delay line 31 30...

Page 419: ...responds to 0x534D43 SMC in ASCII Protects the registers listed below Section 29 16 1 SMC Setup Register Section 29 16 2 SMC Pulse Register Section 29 16 3 SMC Cycle Register Section 29 16 4 SMC MODE...

Page 420: ...on occurred since the last read of the SMC_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write...

Page 421: ...erformance it is advisable to avoid accessing different rows in the same bank The DDRSDRC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency The features of self...

Page 422: ...n by Software CAS Latency of 2 3 Supported Reset Function Supported DDR2 SDRAM ODT On die Termination Not Supported Auto Precharge Command Not Used SDR SDRAM with 16 bit Datapath and Eight Columns Not...

Page 423: ...egrates an arbiter A controller that translates AHB requests Read Write in the SDRAM protocol Memory Controller Finite State Machine SDRAM Signal Management Addr DQM Data Asynchronous Timing Refresh M...

Page 424: ...orm a write access to any SDR SDRAM address to acknowledge this command 6 Eight auto refresh CBR cycles are provided Program the auto refresh command CBR into Mode Register the application must set Mo...

Page 425: ...ed to the low power DDR1 SDRAM Program all banks precharge command into the Mode Register the application must set Mode to 2 in the Mode Register See Section 30 7 1 on page 452 Perform a write access...

Page 426: ...minimum pause of 200 s is provided to precede any signal toggle 4 An NOP command is issued to the DDR2 SDRAM Program the NOP command into the Mode Register the application must set Mode to 1 in the M...

Page 427: ...M loca tion twice to acknowledge these commands 13 Program DLL field into the Configuration Register see Section 30 7 3 on page 454 to low Disable DLL reset 14 A Mode Register set MRS cycle is issued...

Page 428: ...20 Perform a write access to any DDR2 SDRAM address 21 Write the refresh rate into the count field in the Refresh Timer register see page 453 Refresh rate delay between refresh cycles The DDR2 SDRAM...

Page 429: ...he DDRSDRC uses the transfer type signal provided by the master requesting the access If the next access is a sequential write access writing to the SDRAM device is carried out If the next access is a...

Page 430: ...DR1 SDRAM Device Figure 30 3 Single Write Access Row Closed DDR2 SDRAM Device SDCLK A 12 0 COMMAND BA 1 0 0 Row a col a NOP PRCHG NOP ACT NOP WRITE NOP 0 DM 1 0 0 3 Trp 2 Trcd 2 DQS 1 0 D 15 0 Db Da 3...

Page 431: ...e Figure 30 5 Burst Write Access Row Closed Low power DDR1 SDRAM Device Row a Col a 3 0 3 NOP PRCHG NOP ACT NOP WRITE NOP BST SDCLK A 12 0 COMMAND BA 1 0 0 0 DM 1 0 Trp 2 D 31 0 DaDb Trcd 2 Trp 2 Trcd...

Page 432: ...followed by a read command To avoid breaking the current write burst Twtr Twrd bl 2 2 6 cycles should be met See Figure 30 8 on page 433 Trp 2 Trcd 2 SDCLK Row a col a A 12 0 NOP PRCHG NOP ACT NOP WR...

Page 433: ...st be input 1 cycle prior to the read command to avoid writing invalid data See Figure 30 9 on page 433 Figure 30 9 Single Write Access Followed By A Read Access Low power DDR1 SDRAM Devices Twrd BL 2...

Page 434: ...row and initiates a read command To comply with SDRAM timing parameters additional clock cycles are inserted between precharge active Trp commands and active read Trcd command After a read command add...

Page 435: ...locations that can be accessed for a given read command When the read command is issued 8 columns are selected All accesses for that burst take place within these eight columns meaning that the burst...

Page 436: ...SDRAM Device Figure 30 12 Single Read Access Row Close Latency 3 DDR2 SDRAM Device Trp Trcd Latency 2 SDCLK Row a Col a A 12 0 NOP PRCHG NOP ACT NOP READ BST NOP COMMAND 0 BA 1 0 DQS 1 DQS 0 Da Db D...

Page 437: ...ncy 2 SDR SDRAM Device Figure 30 14 Burst Read Access Latency 2 Low power DDR1 SDRAM Devices Row a col a NOP PRCHG NOP ACT NOP READ BST NOP 0 Trp Trcd Latency 2 SDCLK A 12 0 COMMAND BA 1 0 DaDb D 31 0...

Page 438: ...resh commands periodically A timer is loaded with the value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh cycles When the DDRSDRC initiates a refresh of an SDRAM...

Page 439: ...EFRESH command According to the application more AUTO REFRESH commands will be performed when the self refresh mode is enabled during the application This controller also interfaces low power SDRAM Th...

Page 440: ...30 18 Self Refresh Mode Entry Timeout 1 or 2 NOP READ BST NOP PRCHG NOP ARFSH NOP 0 Trp Enter Self refresh Mode SDCLK A 12 0 COMMAND CKE BA 1 0 DQS 0 1 Da Db D 15 0 3 DM 1 0 NOP READ BST NOP 0 Da Db 6...

Page 441: ...TXNRD TXSRD DDR device TXSR Low power DDR1 device TXSR Low power SDR SDR SDRAM device Exit Self Refresh mode clock must be stable before exiting self refresh mode SDCLK A 12 0 COMMAND CKE BA 1 0 DQS...

Page 442: ...tion In order to exit low power mode a NOP command is required in the case of Low power SDR SDRAM and SDR SDRAM devices In the case of Low power DDR1 SDRAM devices the controller generates a NOP comma...

Page 443: ...When this mode is enabled the DDRSDRC leaves normal mode mode 000 and the controller is frozen To exit deep power down mode the low power bits LPCB must be set to 00 an initialization sequence must b...

Page 444: ...t has to de active the last open row and open the new row Two SDRAM commands must be performed to open a bank Pre charge and Active command with respect to Trp timing Before performing a read or write...

Page 445: ...me time the master with the lowest number is serviced first then the others are ser viced in a round robin manner To avoid burst breaking and to provide the maximum throughput for the SDRAM device arb...

Page 446: ...Register DDRSDRC_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Re...

Page 447: ...banks alternate at each SDRAM end page of current bank The DDRSDRC makes the SDRAM devices access protocol transparent to the user Table 30 1 to Table 30 15 illustrate the SDRAM device memory mapping...

Page 448: ...M Configuration 2K Rows 512 1024 2048 4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row 10 0 Bk 1 0 Column 8 0 M0 Row 10 0 Bk 1 0 Column 9 0 M...

Page 449: ...Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk 2 0 Row 12 0 Column 9 0 M0 Table 30 10 Linear Mapping for SDRAM Configuration 16K Rows 1024 Columns CPU Address Line 2...

Page 450: ...0 0 Column 9 0 M 1 0 Bk 1 0 Row 10 0 Column 10 0 M 1 0 Table 30 14 SDR SDRAM Configuration Mapping 4K Rows 256 512 1024 2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 451: ...x7024 0x0C DDRSDRC Timing Parameter 0 Register DDRSDRC_TPR0 Read write 0x20227225 0x10 DDRSDRC Timing Parameter 1 Register DDRSDRC_TPR1 Read write 0x3c80808 0x14 DDRSDRC Timing Parameter 2 Register DD...

Page 452: ...e cycle To activate this mode command must be followed by a write to the SDRAM 010 The DDRSDRC issues an All Banks Precharge command when the SDRAM device is accessed regardless of the cycle To activa...

Page 453: ...aded into a timer which generates the refresh pulse Each time the refresh pulse is generated a refresh sequence is initiated SDRAM devices require a refresh of all rows every 64 ms The value to be loa...

Page 454: ...rotect Mode Register on page 466 NC Number of Column Bits The reset value is 9 column bits SDR SDRAM devices with eight columns in 16 bit mode are not supported NR Number of Row Bits The reset value i...

Page 455: ...trength 1 Weak driver strength This value is used during the power up sequence This parameter is found in the datasheet as DIC or DS Note This field is found only in DDR2 SDRAM devices DIS_DLL Disable...

Page 456: ...set value is 0 0 After an ACTIVE command in Bank X BURST STOP command can be issued to another bank to stop current read access 1 After an ACTIVE command in Bank X BURST STOP command cannot be issued...

Page 457: ...the delay between an Activate Command and a Read Write Command in number of cycles Number of cycles is between 0 and 15 TWR Write Recovery Delay Reset value is 2 cycles This field defines the Write Re...

Page 458: ...the internal write to read command Time in number of cycles Number of cycles is between 1 and 7 REDUCE_WRRD Reduce Write to Read Delay Reset value is 0 This field reduces the delay between write to re...

Page 459: ...s is between 0 and 255 This field is used for SDR SDRAM and DDR SDRAM devices In the case of SDR SDRAM devices and Low power DDR1 SDRAM this field is equivalent to TXSR timing TXSRD ExiT Self Refresh...

Page 460: ...of cycles is between 0 and 15 Note This field is found only in DDR2 SDRAM devices TRPA Row Precharge All Delay The Reset Value is 0 cycle This field defines the delay between a Precharge ALL banks Com...

Page 461: ...Frozen Command Bit Reset value is 0 This field sets the clock low during power down mode or during deep power down mode Some SDRAM devices do not support freezing the clock during power down mode or d...

Page 462: ...accessed automatically and APDE bits are updated In function of the UPD_MR bit update is done before entering in self refresh mode or during a refresh command and a pending read or write access UPD_M...

Page 463: ...DDRSDRC Write Protect Mode Register on page 466 MD Memory Device Indicates the type of memory used Reset value is for SDR SDRAM device 000 SDR SDRAM 001 Low power SDR SDRAM 010 Reserved 011 Low power...

Page 464: ...Delay Decrement 0 The DLL is not decrementing the Master delay counter 1 The DLL is decrementing the Master delay counter MDOVF DLL Master Delay Overflow Flag 0 The Master delay counter has not reache...

Page 465: ...ect Mode Register on page 466 DIS_ANTICIP_READ Anticip Read Access 0 anticip read access is enabled 1 anticip read access is disabled default DIS_ANTICIP_READ allows DDR2 read access optimization with...

Page 466: ...er on page 452 DDRSDRC Refresh Timer Register on page 453 DDRSDRC Configuration Register on page 454 DDRSDRC Timing Parameter 0 Register on page 457 DDRSDRC Timing Parameter 1 Register on page 459 DDR...

Page 467: ...tion has occurred since the last read of the DDRSDRC_WPSR register If this violation is an unau thorized attempt to write a protected register the associated violation is reported into field WPVSRC WP...

Page 468: ...468 11054A ATARM 27 Jul 11 SAM9X25 468 11054A ATARM 27 Jul 11 SAM9X25...

Page 469: ...fers thanks to the 64 word FIFO on channel 0 DMAC1 is optimized for peripheral to memory transfers without PIP support Acting as Two Matrix Masters Embeds 8 unidirectional channels with programmable p...

Page 470: ...ndshaking interface Interrupt Programmable Interrupt generation on DMA Transfer completion Block Transfer completion Single Multiple transaction completion or Error condition 31 2 1 DMA Controller 0 T...

Page 471: ...ween peripherals and memory and so receives the triggers from the peripherals listed below The hardware interface numbers are also given in Table 31 2 TWI0 RX 8 TWI2 TX 9 TWI2 RX 10 UART0 TX 11 UART0...

Page 472: ...destination DMA Channel 1 DMA Channel 2 DMA Channel n External Triggers Soft Triggers DMA REQ ACK Interface Trigger Manager DMA Interrupt Controller Status Registers Configuration Registers Atmel APB...

Page 473: ...ayer Handshaking interface A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or chunk transfe...

Page 474: ...memory device There are two types of transactions single transfer and chunk transfer Single transfer The length of a single transaction is always 1 and is converted to a single AMBA access Chunk tran...

Page 475: ...r when buffer chaining is enabled Replay The DMAC automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled Contiguous buffers Where the ad...

Page 476: ...rent and depends on whether the peripheral or the DMAC is the flow controller The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to trans fer accept data over the A...

Page 477: ...using linked lists is the multi buffer method of choice and on successive buffers the DMAC_DSCRx register in the DMAC is re programmed using the following method Buffer chaining using linked lists A b...

Page 478: ...r is retrieved from memory The last transfer descriptor must be written to memory with its next descriptor address set to 0 Figure 31 5 Multi Buffer Transfer Using Linked List System Memory SADDRx DSC...

Page 479: ...e the address between successive buffers is selected to be a continuation from the end of the previous buffer Enabling the source or destination address to be contiguous between Table 31 3 Multiple Bu...

Page 480: ...r 31 4 4 3 Ending Multi buffer Transfers All multi buffer transfers must end as shown in Row 1 of Table 31 3 on page 479 At the end of every buffer transfer the DMAC samples the row number and if the...

Page 481: ...ording to Row 1 as shown in Table 31 3 on page 479 Program the DMAC_CTRLBx register with both AUTO fields set to 0 e Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTR...

Page 482: ...Write the control information in the LLI DMAC_CTRLAx and LLI DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory see Figure 31 6 on page 484 for channel x For example in the...

Page 483: ...grams the DMAC_SADDRx DMAC_DADDRx DMAC_DSCRx DMAC_CTRLBx and DMAC_CTRLAx chan nel registers from the DMAC_DSCRx 0 15 Source and destination request single and chunk DMAC transactions to transfer the b...

Page 484: ...tion address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx BTSIZE then this can be achieved using the type of multi buffer transfer as sho...

Page 485: ...e and Destination Buffers are Contiguous The DMAC transfer flow is shown in Figure 31 8 on page 486 SADDR 2 SADDR 1 SADDR 0 DADDR 2 DADDR 1 DADDR 0 Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer...

Page 486: ...disabled channel 2 Clear any pending interrupts on the channel from the previous DMAC transfer by read ing the interrupt status register Program the following channel registers Channel enabled by sof...

Page 487: ...han nel x Ensure that the reload bits DMAC_CFGx SRC_REP DMAC_CFGx DST_REP and DMAC_CTRLBx AUTO are enabled i Designate the handshaking interface type hardware or software for the source and destinatio...

Page 488: ...is put the DMAC into Row 1 as shown in Table 31 3 on page 479 If the next buffer is not the last buffer in the DMAC trans fer then the reload bits should remain enabled to keep the DMAC in Row 4 b If...

Page 489: ...nation and flow control peripheral by programming the FC of the DMAC_CTRLBx register b Set up the transfer characteristics such as i Transfer width for the source in the SRC_WIDTH field ii Transfer w...

Page 490: ...location of all LLIs in memory point to the start destination buffer address proceeding that LLI fetch 8 Make sure that the LLI DMAC_CTLx DONE field of the LLI DMAC_CTRLA register locations of all LL...

Page 491: ...and disables the channel You can either respond to the Buffer Complete or Chained buffer Transfer Complete interrupts or poll for the Channel Enable DMAC_CHSR ENABLE bit until it is cleared by hardwa...

Page 492: ...DMAC_CTRLAx DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in Table 31 3 on page 479 Program the DMAC_DSCRx register with 0 DMAC_CTRLBx AUTO field is set to 1 to enable automatic mode support...

Page 493: ...enable the channel by writing a 1 to the DMAC_CHER ENABLE n bit where n is the channel number Make sure that bit 0 of the DMAC_EN ENABLE register is enabled 5 Source and destination request single an...

Page 494: ...rts the next buffer transfer immediately In this case software must clear the automatic mode bit DMAC_CTRLBx AUTO to put the device into ROW 1 of Table 31 3 on page 479 before the last buffer of the D...

Page 495: ...non memory peripheral for source and desti nation and flow control device by programming the FC of the DMAC_CTRLBx register b Set up the transfer characteristics such as i Transfer width for the sour...

Page 496: ...the next Linked List Item 7 Make sure that the LLI DMAC_SADDRx register location of all LLIs in memory point to the start source buffer address proceeding that LLI fetch 8 Make sure that the LLI DMAC...

Page 497: ...rom the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx DMAC_CTRLAx DMAC_CTRLBx and DMAC_DSCRx channel registers The DMAC_DADDRx register is left...

Page 498: ...e disables a channel on transfer com pletion by clearing the DMAC_CHSR ENABLE n register bit The recommended way for software to disable a channel without losing data is to use the SUS PEND n bit in c...

Page 499: ...to receive an acknowledgement 31 4 6 1 Abnormal Transfer Termination A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit DMAC_CHDR ENABLE n where n is the channe...

Page 500: ...f word and word aligned address depending on the source width and destination width After the software disables a channel by writing into the channel disable register it must re enable the channel onl...

Page 501: ...S flag is reset by writing the DMAC Write Protect Mode Register DMAC_WPMR with the appropriate access key WPKEY The protected registers are DMAC Global Configuration Register on page 503 DMAC Enable R...

Page 502: ...DMAC_EBCISR Read only 0x0 0x028 DMAC Channel Handler Enable Register DMAC_CHER Write only 0x02C DMAC Channel Handler Disable Register DMAC_CHDR Write only 0x030 DMAC Channel Handler Status Register DM...

Page 503: ...0x00000010 Note Bit fields 0 1 2 3 have a default value of 0 This should not be changed This register can only be written if the WPEN bit is cleared in DMAC Write Protect Mode Register ARB_CFG Arbite...

Page 504: ...bled 31 7 3 DMAC Software Single Request Register Name DMAC_SREQ Address 0xFFFFEC08 0 0xFFFFEE08 1 Access Read write Reset 0x00000000 DSREQx Request a destination single transfer on channel i SSREQx R...

Page 505: ...0 0xFFFFEE0C 1 Access Read write Reset 0x00000000 DCREQx Request a destination chunk transfer on channel i SCREQx Request a source chunk transfer on channel i 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 506: ...iting one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer SLASTx Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this sourc...

Page 507: ...to enable the interrupt for channel i CBTCx Chained Buffer Transfer Completed 7 0 Chained Buffer Transfer Completed Interrupt Enable Register Set the relevant bit in the CBTC field to enable the inter...

Page 508: ...rrupt from the rele vant DMAC channel CBTCx Chained Buffer Transfer Completed 7 0 Chained Buffer transfer completed Disable Register When set a bit of the CBTC field disables the interrupt from the re...

Page 509: ...r completed interrupt is enabled for channel i CBTCx Chained Buffer Transfer Completed 7 0 0 Chained Buffer Transfer interrupt is disabled for channel i 1 Chained Buffer Transfer interrupt is enabled...

Page 510: ...Channel i buffer transfer has terminated CBTCx Chained Buffer Transfer Completed 7 0 When CBTC i is set Channel i Chained buffer has terminated LLI Fetch operation is disabled ERRx Access Error 7 0 Wh...

Page 511: ...bles the relevant channel SUSPx 7 0 When set a bit of the SUSPfield freezes the relevant channel and its current context KEEPx 7 0 When set a bit of the KEEP field resumes the current channel from an...

Page 512: ...relevant DMAC Channel The content of the FIFO is lost and the current AHB access is terminated Software must poll DIS 7 0 field in the DMAC_CHSR register to be sure that the channel is disabled RESx...

Page 513: ...n of this field indicates that the channel transfer is suspended EMPTx 7 0 A one in any position of this field indicates that the relevant channel is empty STALx 7 0 A one in any position of this fiel...

Page 514: ...FED54 0 7 0xFFFFEE3C 1 0 0xFFFFEE64 1 1 0xFFFFEE8C 1 2 0xFFFFEEB4 1 3 0xFFFFEEDC 1 4 0xFFFFEF04 1 5 0xFFFFEF2C 1 6 0xFFFFEF54 1 7 Access Read write Reset 0x00000000 This register can only be written i...

Page 515: ...D58 0 7 0xFFFFEE40 1 0 0xFFFFEE68 1 1 0xFFFFEE90 1 2 0xFFFFEEB8 1 3 0xFFFFEEE0 1 4 0xFFFFEF08 1 5 0xFFFFEF30 1 6 0xFFFFEF58 1 7 Access Read write Reset 0x00000000 This register can only be written if...

Page 516: ...4 0xFFFFEF0C 1 5 0xFFFFEF34 1 6 0xFFFFEF5C 1 7 Access Read write Reset 0x00000000 This register can only be written if the WPEN bit is cleared in DMAC Write Protect Mode Register DSCR_IF DSCR Buffer...

Page 517: ...e number of transfers to be performed that is for writes it refers to the number of source width transfers to perform when DMAC is flow controller For Reads BTSIZE refers to the number of transfers co...

Page 518: ...000 CHK_1 1 data transferred 001 CHK_4 4 data transferred 010 CHK_8 8 data transferred 011 CHK_16 16 data transferred 100 CHK_32 32 data transferred 101 CHK_64 64 data transferred 110 CHK_128 128 data...

Page 519: ...re in Picture mode is enabled When the source PIP counter reaches the programmable boundary the address is automatically incremented by a user defined amount DST_PIP Destination Picture in Picture Mod...

Page 520: ...tus register This bit is active low AUTO Automatic Multiple Buffer Transfer 0 DISABLE Automatic multiple buffer transfer is disabled 1 ENABLE Automatic multiple buffer transfer is enabled This bit ena...

Page 521: ...TIGUOUS_ADDR When automatic mode is activated source address is contiguous between two buffers 1 RELOAD_ADDR When automatic mode is activated the source address and the control register are reloaded f...

Page 522: ...a chunk transfer 1 BUFFER The Master Interface Arbiter is locked by the channel x for a buffer transfer AHB_PROT AHB_PROT field provides additional information about a bus access and is primarily use...

Page 523: ...FFFFEEF4 1 4 0xFFFFEF1C 1 5 0xFFFFEF44 1 6 0xFFFFEF6C 1 7 Access Read write Reset 0x00000000 This register can only be written if the WPEN bit is cleared in DMAC Write Protect Mode Register SPIP_HOLE...

Page 524: ...0xFFFFEEF8 1 4 0xFFFFEF20 1 5 0xFFFFEF48 1 6 0xFFFFEF70 1 7 Access Read write Reset 0x00000000 This register can only be written if the WPEN bit is cleared in DMAC Write Protect Mode Register DPIP_HOL...

Page 525: ...14 DMAC Channel x x 0 7 Destination Address Register on page 515 DMAC Channel x x 0 7 Descriptor Address Register on page 516 DMAC Channel x x 0 7 Control A Register on page 517 DMAC Channel x x 0 7 C...

Page 526: ...Violation has occurred since the last read of the DMAC_WPSR register If this violation is an unauthor ized attempt to write a protected register the associated violation is reported into field WPVSRC...

Page 527: ...EHCI The USB Host Port controller is fully compliant with the Enhanced HCI specification The USB Host Port User Interface registers description can be found in the Enhanced HCI Rev 1 0 Specification...

Page 528: ...ough the AHB bus slave interface The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as follows Fetches endpoint descript...

Page 529: ...iver is automatically selected for Device operation once the USB High Speed Device is enabled One transceiver is shared with USB Device High Speed In this case USB Host High Speed Controller uses only...

Page 530: ...ks UHP bit in PMC_SCER register For OHCI Full speed operations only the user has to perform the following Enable UHP peripheral clock bit 1 AT91C_ID_UHPHS in PMC_PCER register Select PLLACK as Input c...

Page 531: ...requires programming the AIC before configuring the UHP HS 32 5 Typical Connection Figure 32 4 Board Schematic to Interface UHP High speed Device Controller Note 1 The values shown on the 22k and 15k...

Page 532: ...532 11054A ATARM 27 Jul 11 SAM9X25 532 11054A ATARM 27 Jul 11 SAM9X25...

Page 533: ...e peripheral This feature is mandatory for isochronous endpoints 33 2 Embedded Characteristics 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con...

Page 534: ...which notifies the pro cessor by raising an interrupt Table 33 1 UDPHS Endpoint Description Endpoint Mnemonic Nb Bank DMA High Band Width Max Endpoint Size Endpoint Type 0 EPT_0 1 N N 64 Control 1 EPT...

Page 535: ...gram Figure 33 2 Block Diagram 32 bits System Clock Domain USB Clock Domain Rd Wr Ready APB Interface USB2 0 CORE EPT Alloc AHB1 DMA AHB0 Local AHB Slave interface Master AHB Multiplexeur Slave DPRAM...

Page 536: ...later 33 5 2 Interrupt The UDPHS interrupt line is connected on one of the internal sources of the Interrupt Controller Using the UDPHS interrupt requires the Interrupt Controller to be programmed fir...

Page 537: ...e 33 6 3 USB Transfer Event Definitions A transfer is composed of one or several transactions Notes 1 Control transfer must use endpoints with one bank and can be aborted using a stall handshake 2 Iso...

Page 538: ...the configuration register UDPHS_EPTCFG with the endpoint size direction IN or OUT type CTRL Bulk IT ISO and the number of banks Fill the number of transactions NB_TRANS for isochronous endpoints Not...

Page 539: ...ANK_EPT3 x SIZE_EPT3 NB_BANK_EPT4 x SIZE_EPT4 NB_BANK_EPT5 x SIZE_EPT5 NB_BANK_EPT6 x SIZE_EPT6 refer to 33 7 11 UDPHS Endpoint Configuration Register If a user tries to configure endpoints with a siz...

Page 540: ...itch to the next bank EPT_ENABL Enable endpoint Without DMA TX_BK_RDY An interrupt is generated after each transmission EPT_ENABL Enable endpoint Configuration examples of Bulk OUT endpoint type follo...

Page 541: ...window then slides down and its data is lost Note that the following endpoint memory windows from x 2 do not slide Figure 33 6 on page 541 illustrates the allocation and reorganization of the DPRAM in...

Page 542: ...transferred when required by the UDPHS Device These transfers always feature sequential addressing Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus band width per...

Page 543: ...DPHS_DMA_CHANNEL_NBR 4 i RESET endpoint canal DMA DMA stop channel command AT91C_BASE_UDPHS UDPHS_DMA i UDPHS_DMACONTROL 0 STOP command Disable endpoint AT91C_BASE_UDPHS UDPHS_EPT i UDPHS_EPTCTLDIS 0X...

Page 544: ...hing an interrupt read the setup packet in the FIFO then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage If STALL_SNT was set to 1 then this bit is automatically...

Page 545: ...rite access to the DPR The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window The application sets TX_PK_RDY flag in the UDPHS_EPTSETSTAx register Th...

Page 546: ...UDPHS control The DMA can be used for all transfer types except control transfer Example DMA configuration 1 Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred 2 Enab...

Page 547: ...w transfer descriptor The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is trig gered This can be used to stop DMA transfers in case of errors The application can be...

Page 548: ...SB Bus Packets Set by Hardware Set by Hardware Set by Firmware Data Payload Written in FIFO Bank 0 Written by FIFO DPR Bank1 Microcontroller Written by Microcontroller Written by Microcontroller Micro...

Page 549: ...ration above Autovalid validates a bank as full although this might not be the case in order to continue processing data and to send to DMA Token IN ACK Data OUT Token OUT ACK Data IN USB Bus Packets...

Page 550: ...tted during that microframe shall be flushed at its end If this flush occurs an error condition is flagged ERR_FLUSH is set in UDPHS_EPTSTAx If no bank is validated yet the default DATA0 ZLP is answer...

Page 551: ...have been set in NB_TRANS 33 6 9 9 Data OUT 33 6 9 10 Bulk OUT or Interrupt OUT Like data IN data OUT packets are sent by the host during the data or the status stage of con trol transfer or during an...

Page 552: ...f the USB transfer ended with a short packet Beneficial when the receive size is unknown CHANN_ENB Run and stop at end of buffer For OUT transfer the bank will be automatically cleared by hardware whe...

Page 553: ...ta OUT 3 Token OUT Data OUT 2 Token OUT Data OUT 1 Data OUT 1 Data OUT 2 Data OUT 2 ACK Cleared by Firmware USB Bus Packets Virtual RX_BK_RDY Bank 0 Virtual RX_BK_RDY Bank 1 Set by Hardware Data Paylo...

Page 554: ...han the USB standard then the ISO OUT transaction is ignored Payload data is not written no interrupt is generated to the CPU If there is a data CRC Cyclic Redundancy Check error the payload is none t...

Page 555: ...bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register Figure 33 17 St...

Page 556: ...tus Register UDPHS_INTSTA 33 6 12 Endpoint Interrupts Interrupts are enabled in UDPHS_IEN see Section 33 7 3 UDPHS Interrupt Enable Register and individually masked in UDPHS_EPTCTLENBx see Section 33...

Page 557: ...CTLENBx NAK_IN ERR_FLUSH STALL_SNT ERR_CRISO ERR_NBTRA RX_SETUP ERR_FL_ISO TX_BK_RDY ERR_TRANS TX_COMPLT RX_BK_RDY ERR_OVFLW MDATA_RX DATAX_RX UDPHS_IEN EPT1 6 IT Sources Global IT mask Global IT sour...

Page 558: ...ts from the USB host is mandatory Constraints in Suspend Mode are very strict for bus powered applications devices may not consume more than 500 A on the USB bus While in Suspend Mode the host may wak...

Page 559: ...et in the UDPHS_IEN register and an interrupt is triggered Once the ENDRESET interrupt has been triggered the device enters Default State In this state the UDPHS software must Enable the default endpo...

Page 560: ...e board The UDPHS device peripheral clocks can be switched off Resume event is asynchronously detected 33 6 13 8 Receiving a Host Resume In Suspend mode a resume event on the USB bus line is detected...

Page 561: ...See Section 33 7 7 UDPHS Test Register on page 572 for definitions of each test mode const char test_packet_buffer 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 JKJKJKJK 9 0xAA 0xAA 0xAA 0xAA 0xAA 0xAA...

Page 562: ..._0000 0xE4 0xE8 Reserved 0xF0 UDPHS Name1 Register UDPHS_IPNAME1 Read only 0x4855_5342 0xF4 UDPHS Name2 Register UDPHS_IPNAME2 Read only 0x3244_4556 0xF8 UDPHS Features Register UDPHS_IPFEATURES Read...

Page 563: ..._UDPHS UDPHS Enable 0 UDPHS is disabled read or this bit disables and resets the UDPHS controller write Switch the host to UTMI 1 UDPHS is enabled read or this bit enables the UDPHS controller write S...

Page 564: ...DP Pull Down 0 Note If the DETACH bit is also set device DP DM are left in high impedance state See DETACH description above DETACH PULLD_DIS DP DM Condition 0 0 Pull up Pull down not recommended 0 1...

Page 565: ...croseconds 1 ms 8 FRAME_NUMBER Frame Number as defined in the Packet Field Formats This field is provided in the last received SOF packet see INT_SOF in the UDPHS Interrupt Status Register FNUM_ERR Fr...

Page 566: ...rupt Enable 0 disable End Of Reset Interrupt 1 enable End Of Reset Interrupt Automatically enabled after USB reset WAKE_UP Wake Up CPU Interrupt Enable 0 disable Wake Up CPU Interrupt 1 enable Wake Up...

Page 567: ...Jul 11 SAM9X25 EPT_x Endpoint x Interrupt Enable 0 disable the interrupts for this endpoint 1 enable the interrupts for this endpoint DMA_x DMA Channel x Interrupt Enable 0 disable the interrupts for...

Page 568: ...E_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn t change Note The Micro Start Of Frame Interrupt MICRO_SOF and the Start Of Frame Interrupt INT_SOF are not generated...

Page 569: ...when the UDPHS controller detects a good end of resume signal initiated by the host This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN UPSTR_RES Upstream Resume Interrupt 0 clea...

Page 570: ...rupt Clear 0 no effect 1 clear the INT_SOF bit in UDPHS_INTSTA ENDRESET End Of Reset Interrupt Clear 0 no effect 1 clear the ENDRESET bit in UDPHS_INTSTA WAKE_UP Wake Up CPU Interrupt Clear 0 no effec...

Page 571: ...ddress 0xF803C01C Access Write only EPT_x Endpoint x Reset 0 no effect 1 reset the Endpointx state Setting this bit clears the Endpoint status UDPHS_EPTSTAx register except for the TOGGLESQ_STA field...

Page 572: ...mes eye pat terns jitter and any other dynamic waveform specifications OPMODE2 OpMode2 0 no effect 1 set to force the OpMode signal UTMI interface to 10 to disable the bit stuffing and the NRZI encodi...

Page 573: ...eed receive mode and remain in that mode until the exit action is taken This enables the testing of output impedance low level output voltage and loading characteristics In addition while in this mode...

Page 574: ...27 Jul 11 SAM9X25 33 7 8 UDPHS Name1 Register Name UDPHS_IPNAME1 Address 0xF803C0F0 Access Read only IP_NAME1 ASCII string HUSB 31 30 29 28 27 26 25 24 IP_NAME1 23 22 21 20 19 18 17 16 IP_NAME1 15 14...

Page 575: ...27 Jul 11 SAM9X25 33 7 9 UDPHS Name2 Register Name UDPHS_IPNAME2 Address 0xF803C0F4 Access Read only IP_NAME2 ASCII string 2DEV 31 30 29 28 27 26 25 24 IP_NAME2 23 22 21 20 19 18 17 16 IP_NAME2 15 14...

Page 576: ...hardware implemented 2 if 2 DMA channels are hardware implemented 7 if 7 DMA channels are hardware implemented DMA_B_SIZ DMA Buffer Size 0 if the DMA Buffer size is 16 bits 1 if the DMA Buffer size is...

Page 577: ...DPRAM is 16384 bytes deep BW_DPRAM DPRAM Byte Write Capability 0 if DPRAM Write Data Shadow logic is implemented 1 if DPRAM is byte write capable DATAB16_8 UTMI DataBus16_8 0 if the UTMI uses an 8 bit...

Page 578: ...his bit to configure OUT direction for Bulk Interrupt and Isochronous endpoints 1 set this bit to configure IN direction for Bulk Interrupt and Isochronous endpoints For Control endpoints this bit has...

Page 579: ...ped 0 the user should reprogram the register with correct values 1 set by hardware when the endpoint size EPT_SIZE and the number of banks BK_NUMBER are correct regarding the fifo max capacity FIFO_MA...

Page 580: ...pts Disable DMA 0 no effect 1 If set when an enabled endpoint originated interrupt is triggered the DMA request is disabled NYET_DIS NYET Disable Only for High Speed Bulk OUT endpoints 0 no effect 1 f...

Page 581: ...ffect 1 enable RX_SETUP Error Flow ISO Interrupt STALL_SNT ERR_CRISO ERR_NBTRA Stall Sent ISO CRC Error Number of Transaction Error Interrupt Enable 0 no effect 1 enable Stall Sent Error CRC ISO Error...

Page 582: ...DMA 0 no effect 1 disable the Interrupts Disable DMA NYET_DIS NYET Enable Only for High Speed Bulk OUT endpoints 0 no effect 1 let the hardware handle the handshake response for the High Speed Bulk OU...

Page 583: ...ived SETUP Error Flow Interrupt Disable 0 no effect 1 disable RX_SETUP Error Flow ISO Interrupt STALL_SNT ERR_CRISO ERR_NBTRA Stall Sent ISO CRC Error Number of Transaction Error Interrupt Disable 0 n...

Page 584: ...wants to send a Zero Length Packet by software For OUT Transfer If this bit is set then the UDPHS_EPTSTAx register RX_BK_RDY bit is automatically reset for the current bank when the last packet byte...

Page 585: ...pt Enabled Only for High Bandwidth Isochronous OUT endpoints 0 no effect 1 send an interrupt when a DATA2 DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been rec...

Page 586: ...s enabled NAK_OUT NAKOUT Interrupt Enabled 0 NAKOUT Interrupt is masked 1 NAKOUT Interrupt is enabled BUSY_BANK Busy Bank Interrupt Enabled 0 BUSY_BANK Interrupt is masked 1 BUSY_BANK Interrupt is ena...

Page 587: ...et 0 no effect 1 set this bit after a packet has been written into the endpoint FIFO for IN data transfers This flag is used to generate a Data IN transaction device to host Device firmware checks tha...

Page 588: ...ould be a DATA0 For IN endpoints the next packet will be sent with a DATA0 PID RX_BK_RDY Received OUT Data Clear 0 no effect 1 clear the RX_BK_RDY flag of UDPHS_EPTSTAx TX_COMPLT Transmitted IN Data C...

Page 589: ...SAM9X25 589 11054A ATARM 27 Jul 11 SAM9X25 NAK_IN ERR_FLUSH NAKIN Bank Flush Error Clear 0 no effect 1 clear the NAK_IN ERR_FLUSH flags of UDPHS_EPTSTAx NAK_OUT NAKOUT Clear 0 no effect 1 clear the NA...

Page 590: ...current bank is busy Received OUT Data 1 2 These bits are updated for OUT transfer a new data has been written into the current bank the user has just cleared the Received OUT Data bit to switch to t...

Page 591: ...s sent on the UDPHS line In this case the TX_COMPLT bit is set Take notice however that if at least two banks are ready to be sent there is no problem to kill a packet even if an IN token is coming In...

Page 592: ...eset endpoint and by UDPHS_EPTCTLDISx disable endpoint STALL_SNT ERR_CRISO ERR_NBTRA Stall Sent CRC ISO Error Number of Transaction Error STALL_SNT for Control Bulk and Interrupt endpoints This bit is...

Page 593: ...st 1 a Control Read is requested by the Host Notes 1 This bit corresponds with the 7th bit of the bmRequestType Byte 0 of the Setup Data 2 This bit is updated after receiving new setup data BUSY_BANK_...

Page 594: ...ket An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size This bit is updated at the same time as the BYTE_COUNT field This bit is res...

Page 595: ...Register UDPHS_DMANXTDSCx Offset 4 The address must be aligned 0xXXXX4 DMA Channelx Address Register UDPHS_DMAADDRESSx Offset 8 The address must be aligned 0xXXXX8 DMA Channelx Control Register UDPHS_...

Page 596: ...20 2 0xF803C330 3 0xF803C340 4 0xF803C350 5 Access Read write Note Channel 0 is not used NXT_DSC_ADD This field points to the next channel descriptor to be processed This channel descriptor must be al...

Page 597: ...ss to the AHB bus It is incrementing of the access byte width The access width is 4 bytes or less at packet start or end if the start or end address is not aligned on a word boundary The packet start...

Page 598: ...s currently serviced when this bit is cleared the DMA FIFO buffer is drained until it is empty then the UDPHS_DMASTATUS register CHANN_ENB bit is cleared If the LDNXT_DSC bit is set at or after this b...

Page 599: ...hing end of buffer but could be used for OUT packet truncation discarding of unwanted packet data at the end of DMA buffer END_TR_IT End of Transfer Interrupt Enable 0 UDPHS device initiated buffer tr...

Page 600: ...wn this field should be set to 0 but the transfer end may occur earlier under UDPHS device control When this field is written The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write v...

Page 601: ...is drained until it is empty then this status bit is cleared CHANN_ACT Channel Active Status 0 the DMA channel is no longer trying to source the packet data When a packet transfer is ended this bit i...

Page 602: ...om the AHB source bus access byte width at the end of this bus address phase The access byte width is 4 by default or less at DMA start or end if the start or end address is not aligned on a word boun...

Page 603: ...m mand one data three power lines and one reserved for future use The SD Memory Card interface also supports High Speed MultiMedia Card operations The main differences between SD and High Speed MultiM...

Page 604: ...11054A ATARM 27 Jul 11 SAM9X25 34 3 Block Diagram Figure 34 1 Block Diagram HSMCI Interface Interrupt Control PIO DMAC APB Bridge PMC MCK HSMCI Interrupt MCCK 1 MCCDA 1 MCDA0 1 MCDA1 1 MCDA2 1 MCDA3 1...

Page 605: ...o HSMCIx_CDA MCDAy to HSMCIx_DAy 2 3 4 5 6 1 7 MMC 2 3 4 5 6 1 78 SDCard 9 Physical Layer HSMCI Interface Application Layer ex File System Audio Security etc 9 1011 1213 8 Table 34 1 I O Lines Descrip...

Page 606: ...he PMC to enable the HSMCI clock 34 6 3 Interrupt The HSMCI interface has an interrupt line connected to the Advanced Interrupt Controller AIC Handling the HSMCI interrupt requires programming the AIC...

Page 607: ...CCK refers to HSMCIx_CK MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy Table 34 4 Bus Topology Pin Number Name Type 1 Description HSMCI Pin Name 2 Slot z 1 DAT 3 I O PP Data MCDz3 2 CMD I O PP OD Command res...

Page 608: ...to HSMCIx_CK MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy Table 34 5 SD Memory Card Bus Signals Pin Number Name Type 1 Description HSMCI Pin Name 2 Slot z 1 CD DAT 3 I O PP Card detect Data line Bit 3 MCDz...

Page 609: ...to the host as an answer to a previously received command A response is transferred serially on the CMD line Data Data can be transferred from the card to the host or vice versa Data is transferred v...

Page 610: ...full This will guar antee data integrity not bandwidth All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMediaCard System Specification The two bus modes open drain and...

Page 611: ...mand requires a response it can be read in the HSMCI response register HSMCI_RSPR The response size can be from 48 bits up to 136 bits depending on the com mand The HSMCI embeds an error detection to...

Page 612: ...the High Speed MultiMe dia Card specification RETURN OK RETURN ERROR 1 RETURN OK Set the command argument HSMCI_ARGR Argument 1 Set the command HSMCI_CMDR Command Read HSMCI_SR CMDRDY Status error fl...

Page 613: ...blocks until a stop transmission command is received Multiple block read or write with pre defined block count since version 3 1 and higher The card will transfer or program the requested number of da...

Page 614: ...d data HSMCI_RDR Number of words to read Number of words to read 1 Send READ_SINGLE_BLOCK command 1 Yes Set the DMAEN bit HSMCI_DMA DMAEN Set the block length in bytes HSMCI_BLKR BlockLength 16 2 Conf...

Page 615: ...bit PADV is 0 then 0x00 value is used when padding data otherwise 0xFF is used If set the bit DMAEN in the HSMCI_DMA register enables DMA transfer The following flowchart Figure 34 9 shows how to writ...

Page 616: ...to write DMAC_BTSIZE BlockLength 4 Send WRITE_SINGLE_BLOCK command 1 Read status register HSMCI_SR Poll the bit XFRDONE 0 Yes No Yes No Read status register HSMCI_SR Number of words to write 0 Poll th...

Page 617: ...mmand has been correctly sent see Figure 34 7 2 Handle errors reported in HSMCI_SR Send SELECT DESELECT_CARD command 1 to select the card Send SET_BLOCKLEN command 1 Set the block length HSMCI_MR Bloc...

Page 618: ...porary value called dma_offset The two LSB bits of DMAC_SADDRx must be set to 0 e The DMAC_DADDRx register for channel x must be set with the starting address of the HSMCI_FIFO address f Program DMAC_...

Page 619: ...m the previous DMA transfer by reading the DMAC_EBCISR register c Program the channel registers d The DMAC_SADDRx register for channel x must be set with the starting address of the HSMCI_FIFO address...

Page 620: ...ess of the HSMCI_FIFO address e The LLI_W DMAC_DADDRx field in the memory must be word aligned f Program LLI_W DMAC_CTRLAx with the following field s values DST_WIDTH is set to WORD SRC_WIDTH is set t...

Page 621: ...iptor fetch is disabled or Next descriptor location points to 0 DIF and SIF are set with their respective layer ID If SIF is different from DIF DMA Controller is able to prefetch data and write HSMCI...

Page 622: ...refetch data and write HSMCI simultaneously h Program DMAC_CFGx register for channel x with the following field s values FIFOCFG defines the watermark of the DMA channel FIFO SRC_H2SEL is set to true...

Page 623: ...ination SRC_DSCR is set to 1 source address is contiguous FC field is programmed with memory to peripheral flow control mode Both DST_DSCR and SRC_DSCR are set to 1 descriptor fetch is disabled DIF an...

Page 624: ...any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register c Program the channel registers in the Memory with the first descriptor This descrip tor will b...

Page 625: ...the HSMCI_ARG then the HSMCI_CMDR 12 Wait for XFRDONE in HSMCI_SR register 34 8 8 2 Block Length is Not Multiple of 4 ROPT field in HSMCI_DMA register set to 0 Two DMA Transfer descriptors are used to...

Page 626: ...channel registers in the Memory for the second descriptor This descriptor will be byte oriented This descriptor is referred to as LLI_B n standing for LLI Byte oriented l The LLI_B n DMAC_SADDRx fiel...

Page 627: ...value to the nearest multiple of 4 1 Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK 2 Set the ROPT field to 1 in the HSMCI_DMA register 3 Issue a READ_MULTIPLE_BLOCK co...

Page 628: ...eck and handle HSMCI errors 7 Poll FIFOEMPTY field in the HSMCI_SR 8 Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR 9 Wait for XFRDONE in HSMCI_SR register 34 9 SD SDIO C...

Page 629: ...spend resume Refer to the SDIO Specification for more details To send a suspend or a resume command the host must set the SDIO Special Command field IOSPCMD in the HSMCI Command Register 34 9 2 SDIO I...

Page 630: ...onditions are expected to happen infrequently Thus a robust error recovery mechanism may be used for each error event The recommended error recovery procedure after a timeout is Issue the command comp...

Page 631: ...asserted 6 When Data transfer is completed host processor shall terminate the boot stream by writing the HSMCI_CMDR register with SPCMD field set to BOOTEND 34 11 2 Boot Procedure DMA Mode 1 Configur...

Page 632: ...MD line HSMCI read CMD Card response CMDRDY flag Data 1st Block Last Block Not busy flag XFRDONE flag The CMDRDY flag is released 8 tbit after the end of the card response CMD line Card response CMDRD...

Page 633: ...to 0x00FC is detected then the WPVS flag in the HSMCI Write Protect Status Register HSMCI_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag...

Page 634: ...ead write 0x0 0x20 Response Register 1 HSMCI_RSPR Read 0x0 0x24 Response Register 1 HSMCI_RSPR Read 0x0 0x28 Response Register 1 HSMCI_RSPR Read 0x0 0x2C Response Register 1 HSMCI_RSPR Read 0x0 0x30 R...

Page 635: ...Power Save Mode Enable 0 No effect 1 Enables the Power Saving Mode if PWSDIS is 0 Warning Before enabling this mode the user must set a value different from 0 in the PWSDIV field Mode Register HSMCI_...

Page 636: ...ad Proof Enable Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full This will guarantee data integrity not bandwidth 0 Disables Read Proof 1 Enables Read...

Page 637: ...is used when padding data in write transfer 1 0xFF value is used when padding data in write transfer PADV may be only in manual transfer CLKODD Clock divider is odd This field is the least significan...

Page 638: ...two data block trans fers It equals DTOCYC x Multiplier DTOMUL Data Timeout Multiplier Multiplier is defined by DTOMUL as shown in the following table If the data time out set by DTOCYC and DTOMUL ha...

Page 639: ...en if the WPEN bit is cleared in HSMCI Write Protect Mode Register on page 660 SDCSEL SDCard SDIO Slot SDCBUS SDCard SDIO Bus Width 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 640: ...M9X25 34 14 5 HSMCI Argument Register Name HSMCI_ARGR Address 0xF0008010 0 0xF000C010 1 Access Read write ARG Command Argument 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 ARG 15 14 13 12 11 10...

Page 641: ...ACK ATACS IOSPCMD 23 22 21 20 19 18 17 16 TRTYP TRDIR TRCMD 15 14 13 12 11 10 9 8 MAXLAT OPDCMD SPCMD 7 6 5 4 3 2 1 0 RSPTYP CMDNB Value Name Description 0 NORESP No response 1 48_BIT 48 bit response...

Page 642: ...tion Request Start a boot operation mode the host processor can read boot data from the MMC device directly 7 EBO End Boot Operation This command allows the host processor to terminate the boot operat...

Page 643: ...The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued When set to one this field indicates that a Boot acknowledge is expected within a programmab...

Page 644: ...ata Block Length This field determines the size of the data block This field is also accessible in the HSMCI Mode Register HSMCI_MR Bits 16 and 17 must be set to 0 if FBYTE is disabled Note In SDIO By...

Page 645: ...ier These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer and the assertion of the completion signal The data transfer comprises da...

Page 646: ...MCI_RSPR or at consecutive addresses 0x20 to 0x2C N depends on the size of the response 34 14 10 HSMCI Receive Data Register Name HSMCI_RDR Address 0xF0008030 0 0xF000C030 1 Access Read only DATA Data...

Page 647: ...25 34 14 11 HSMCI Transmit Data Register Name HSMCI_TDR Address 0xF0008034 0 0xF000C034 1 Access Write only DATA Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11...

Page 648: ...us Refer to the MMC or SD Specification for more details concerning the CRC Status DTIP Data Transfer in Progress 0 No data transfer in progress 1 The current data transfer is still in progress includ...

Page 649: ...pt on Slot A occurred Cleared when reading the HSMCI_SR SDIOWAIT SDIO Read Wait Operation Status 0 Normal Bus operation 1 The data bus has entered IO wait state CSRCV CE ATA Completion Signal Received...

Page 650: ...over run is raised Cleared by reading in the HSMCI_SR register DMADONE DMA Transfer done 0 DMA buffer transfer has not completed since the last read of HSMCI_SR register 1 DMA buffer transfer has comp...

Page 651: ...0 No error 1 At least one 8 bit data has been sent without valid information not written Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1 When FERRCTRL in HS...

Page 652: ...Interrupt Enable CSRCV Completion Signal Received Interrupt Enable RINDE Response Index Error Interrupt Enable RDIRE Response Direction Error Interrupt Enable RCRCE Response CRC Error Interrupt Enable...

Page 653: ...le FIFOEMPTY FIFO empty Interrupt enable XFRDONE Transfer Done Interrupt enable ACKRCV Boot Acknowledge Interrupt Enable ACKRCVE Boot Acknowledge Error Interrupt Enable OVRE Overrun Interrupt Enable U...

Page 654: ...terrupt Disable RINDE Response Index Error Interrupt Disable RDIRE Response Direction Error Interrupt Disable RCRCE Response CRC Error Interrupt Disable RENDE Response End Bit Error Interrupt Disable...

Page 655: ...errupt Disable XFRDONE Transfer Done Interrupt Disable ACKRCV Boot Acknowledge Interrupt Disable ACKRCVE Boot Acknowledge Error Interrupt Disable OVRE Overrun Interrupt Disable UNRE Underrun Interrupt...

Page 656: ...Interrupt Mask RINDE Response Index Error Interrupt Mask RDIRE Response Direction Error Interrupt Mask RCRCE Response CRC Error Interrupt Mask RENDE Response End Bit Error Interrupt Mask RTOE Respons...

Page 657: ...nsfer Done Interrupt Mask ACKRCV Boot Operation Acknowledge Received Interrupt Mask ACKRCVE Boot Operation Acknowledge Error Interrupt Mask OVRE Overrun Interrupt Mask UNRE Underrun Interrupt Mask 0 T...

Page 658: ...asserted DMAEN DMA Hardware Handshaking Enable 0 DMA interface is disabled 1 DMA Interface is enabled Note To avoid unpredictable behavior DMA hardware handshaking must be disabled when CPU transfers...

Page 659: ...ount of data is written in the internal FIFO 1 A write transfer starts as soon as one data is written into the FIFO FERRCTRL Flow Error flag reset control mode 0 When an underflow overflow condition f...

Page 660: ...ite Protection Key password Should be written at value 0x4D4349 ASCII code for MCI Writing any other value in this field has no effect Protects the registers HSMCI Mode Register on page 636 HSMCI Data...

Page 661: ...ttempted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP_VSRC 15 14 13 12 11 10 9 8 WP_VSRC 7 6 5 4 3 2 1 0 WP_VS Value Name Description 0 NONE No Write Protection Violation occurred since the last...

Page 662: ...SMCI FIFOx Memory Aperture Name HSMCI_FIFOx x 0 255 Address 0xF0008200 0 0xF000C200 1 Access Read write DATA Data to Read or Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15...

Page 663: ...Out Slave In MOSI This data line supplies the output data from the master shifted into the input s of the slave s Master In Slave Out MISO This data line supplies the output data from a slave to the i...

Page 664: ...AM9X25 664 11054A ATARM 27 Jul 11 SAM9X25 35 3 Block Diagram Figure 35 1 Block Diagram SPI Interface Interrupt Control PIO Peripheral Bridge DMA Ch AHB Matrix PMC MCK SPI Interrupt SPCK MISO MOSI NPCS...

Page 665: ...s to their peripheral functions 35 6 2 Power Management The SPI may be clocked through the Power Management Controller PMC thus the program mer must first configure the PMC to enable the SPI clock Tab...

Page 666: ...ata transfers are identically programmable for both modes of operations The baud rate generator is activated only in Master Mode 35 7 2 Data Transfer Four combinations of polarity and phase are availa...

Page 667: ...mmable baud rate generator It fully controls the data transfers to and from the slave s 6 SPCK CPOL 0 SPCK CPOL 1 MOSI from master MISO from slave NSS to slave SPCK cycle for reference MSB MSB LSB LSB...

Page 668: ...d shifted in the Shift Register Transmission cannot occur without reception Before writing the TDR the PCS field must be set in order to select a slave If new data is written in SPI_TDR during the tra...

Page 669: ...5 Master Mode Block Diagram Shift Register SPCK MOSI LSB MSB MISO SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0 3 CPOL NCPHA BITS MCK Baud Rate Generator SPI_CSR0 3 SCBR NPCS3 NPCS0 NPCS2...

Page 670: ...RD Serializer RDRF 1 TDRE NPCS 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT 0 1 CSAAT 0 TDRE 1 0 PS 0 1 SPI_TDR PCS NPCS no yes SPI_MR PCS NPCS no NPCS 0xF Delay DLYBCS NPCS SPI_...

Page 671: ...sults At reset SCBR is 0 and the user has to program it at a valid value before performing the first transfer The divisor can be defined independently for each chip select as it has to be programmed i...

Page 672: ...e Peripheral Select Data can be exchanged with more than one peripheral without having to reprogram the NPCS field in the SPI_MR register Variable Peripheral Select is activated by setting PS bit to o...

Page 673: ...can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines NPCS0 to NPCS3 with 1 of up to 16 decoder demultiplexer This can be enabled by writing the PCSDEC bit a...

Page 674: ...transfers might lead to communication errors To facilitate interfacing with such devices the Chip Select Register CSR0 CSR3 can be pro grammed with the CSAAT bit Chip Select Active After Transfer at 1...

Page 675: ...level is driven by an external master on the NPCS0 NSS signal In this case multi master configuration NPCS0 MOSI MISO and SPCK pins must be configured in open drain through the PIO control ler When a...

Page 676: ...SPI_RDR The user has to read the status register to clear the OVRES bit When a transfer starts the data shifted out is the data present in the Shift Register If no data has been written in the Transm...

Page 677: ...ion Mode Register SPI_WPMR If a write access in a write protected register is detected then the SPIWPVS flag in the SPI Write Protection Status Register SPI_WPSR is set and the field SPIWPVSRC indicat...

Page 678: ..._SR Read only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write only 0x18 Interrupt Disable Register SPI_IDR Write only 0x1C Interrupt Mask Register SPI_IMR Read only 0x0 0x20 0x2C Reserved 0x30...

Page 679: ...control register is written the SPI is disabled SWRST SPI Software Reset 0 No effect 1 Reset the SPI A software triggered hardware reset of the SPI interface is performed The SPI is in slave mode aft...

Page 680: ...p selects according to the following rules SPI_CSR0 defines peripheral chip select signals 0 to 3 SPI_CSR1 defines peripheral chip select signals 4 to 7 SPI_CSR2 defines peripheral chip select signals...

Page 681: ...1 PCS x011 NPCS 3 0 1011 PCS 0111 NPCS 3 0 0111 PCS 1111 forbidden no peripheral is selected x don t care If PCSDEC 1 NPCS 3 0 output signals PCS DLYBCS Delay Between Chip Selects This field defines t...

Page 682: ...er right justified Unused bits read zero PCS Peripheral Chip Select In Master Mode only these bits indicate the value on the NPCS pins at the end of a transfer Otherwise these bits read zero Note When...

Page 683: ...EC 0 PCS xxx0 NPCS 3 0 1110 PCS xx01 NPCS 3 0 1101 PCS x011 NPCS 3 0 1011 PCS 0111 NPCS 3 0 0111 PCS 1111 forbidden no peripheral is selected x don t care If PCSDEC 1 NPCS 3 0 output signals PCS LASTX...

Page 684: ...t Error 0 No Mode Fault has been detected since the last read of SPI_SR 1 A Mode Fault occurred since the last read of the SPI_SR OVRES Overrun Error Status 0 No overrun has been detected since the la...

Page 685: ...orresponding interrupt RDRF Receive Data Register Full Interrupt Enable TDRE SPI Transmit Data Register Empty Interrupt Enable MODF Mode Fault Error Interrupt Enable OVRES Overrun Error Interrupt Enab...

Page 686: ...responding interrupt RDRF Receive Data Register Full Interrupt Disable TDRE SPI Transmit Data Register Empty Interrupt Disable MODF Mode Fault Error Interrupt Disable OVRES Overrun Error Interrupt Dis...

Page 687: ...led 1 The corresponding interrupt is enabled RDRF Receive Data Register Full Interrupt Mask TDRE SPI Transmit Data Register Empty Interrupt Mask MODF Mode Fault Error Interrupt Mask OVRES Overrun Erro...

Page 688: ...CK NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured NCPHA is used with CPOL to produce the required clock data relationship between master and slave...

Page 689: ...any value DLYBS Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition When DLYBS equals zero the NPCS valid to SPCK transition is 1 2 the SPCK clock period...

Page 690: ...ection Enable 0 The Write Protection is Disabled 1 The Write Protection is Enabled SPIWPKEY SPI Write Protection Key Password If a value is written in SPIWPEN the value is taken into account only if S...

Page 691: ...tion enabled have occurred since the last read 0x4 Write accesses have been detected on SPI_MR while a chip select was active or on SPI_CSRi while the Chip Select i was active since the last read 0x5...

Page 692: ...692 11054A ATARM 27 Jul 11 SAM9X25 692 11054A ATARM 27 Jul 11 SAM9X25...

Page 693: ...frequency measurement event counting interval measurement pulse generation delay timing and pulse width modulation Each channel has three external clock inputs five internal clock inputs and two multi...

Page 694: ...OB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA0 TIOA1 Interrupt Controller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 T...

Page 695: ...d a 32 bit counter The value of the counter is incremented at each positive edge of the selected clock When the counter has reached the value 0xFFFF and passes to 0x0000 an overflow occurs and the COV...

Page 696: ...efines this signal none XC0 XC1 XC2 See Figure 36 3 Clock Selection Note In all cases if an external clock is used the duration of each of its levels must be longer than the master clock period The ex...

Page 697: ...ent if CPCDIS is set to 1 in TC_CMR When disabled the start or the stop actions have no effect only a CLKEN command in the Control Register can re enable the clock When the clock is enabled the CLKSTA...

Page 698: ...be read differently from zero just after a trigger especially when a low frequency signal is selected as the clock The following triggers are common to both modes Software Trigger Each channel has a...

Page 699: ...le event occurs on the signal TIOA The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A and the LDRB parameter defines the TIOA edge for the loading of Register B RA is loa...

Page 700: ...CLKSTA CLKEN CLKDIS BURST TIOB Register C Capture Register A Capture Register B Compare RC Counter ABETRG SWTRG ETRGEDG CPCTRG TC1_IMR Trig LDRBS LDRAS ETRGS TC1_SR LOVRS COVFS SYNC 1 MTIOB TIOA MTIOA...

Page 701: ...this mode TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event EEVT parameter in TC_CMR Figure 36 6 shows the configuration of the TC channel when pr...

Page 702: ...A Compare RB Compare RC CPCSTOP Counter EEVT EEVTEDG SYNC SWTRG ENETRG WAVSEL TC1_IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS TC1_SR CPCS CPBS CLK OVF...

Page 703: ...rnal event trigger or a software trigger can reset the value of TC_CV It is important to note that the trigger may occur at any time See Figure 36 8 RC Compare cannot be programmed to generate a trigg...

Page 704: ...tant to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly See Figure 36 10 In addition RC Compare can stop the counter clock CPCSTOP...

Page 705: ...nal event or a software trigger can modify TC_CV at any time If a trig ger occurs while TC_CV is incrementing TC_CV then decrements If a trigger is received while TC_CV is decrementing TC_CV then incr...

Page 706: ...tware trigger can modify TC_CV at any time If a trig ger occurs while TC_CV is incrementing TC_CV then decrements If a trigger is received while TC_CV is decrementing TC_CV then increments See Figure...

Page 707: ...gure 36 14 WAVSEL 11 With Trigger Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with RC 0xFFFF Waveform Examples Time Counter Value TIOB TIOA Counter decremented by compar...

Page 708: ...rate waveforms and subsequently no IRQs In this case the TC channel can only generate a waveform on TIOA When an external event is defined it can be used as a trigger by setting bit ENETRG in TC_CMR A...

Page 709: ...Reserved 0x00 channel 0x40 0x10 Counter Value TC_CV Read only 0 0x00 channel 0x40 0x14 Register A TC_RA Read write 2 0 0x00 channel 0x40 0x18 Register B TC_RB Read write 2 0 0x00 channel 0x40 0x1C Re...

Page 710: ...gister Name TC_BCR Address 0xF80080C0 0 0xF800C0C0 1 Access Write only SYNC Synchro Command 0 no effect 1 asserts the SYNC signal which generates a software trigger simultaneously for each of the chan...

Page 711: ...20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2XC2S TC1XC1S TC0XC0S Value Name Description 0 TCLK0 Signal connected to XC0 TCLK0 1 Reserved 2 TIOA1 Signal connected to XC0 TIOA1 3 TIOA2 Sign...

Page 712: ...0C080 1 2 Access Write only CLKEN Counter Clock Enable Command 0 no effect 1 enables the clock if CLKDIS is not 1 CLKDIS Counter Clock Disable Command 0 no effect 1 disables the clock SWTRG Software T...

Page 713: ...when RB loading occurs 1 counter clock is stopped when RB loading occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG ABETRG ETRGEDG 7 6 5 4 3 2 1 0 LDBD...

Page 714: ...Compare has no effect on the counter and its clock 1 RC Compare resets the counter and starts the counter clock WAVE 0 Capture Mode is enabled 1 Capture Mode is disabled Waveform Mode is enabled LDRA...

Page 715: ...RC 1 counter clock is stopped when counter reaches RC 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL ENETRG EEVT EEVTED...

Page 716: ...ct on the counter and its clock In this case the selected external event only controls the TIOA output 1 the external event resets the counter and starts the counter clock WAVSEL Waveform Selection WA...

Page 717: ...BCPB RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Descrip...

Page 718: ...BEEVT External Event Effect on TIOB BSWTRG Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Value Name Description 0 NONE None 1 SET Set 2 CL...

Page 719: ...counter value in real time 36 7 7 TC Register A Name TC_RAx x 0 2 Address 0xF8008014 0 0 0xF8008054 0 1 0xF8008094 0 2 0xF800C014 1 0 0xF800C054 1 1 0xF800C094 1 2 Access Read only if WAVE 0 Read wri...

Page 720: ...ter B RB contains the Register B value in real time 36 7 9 TC Register C Name TC_RCx x 0 2 Address 0xF800801C 0 0 0xF800805C 0 1 0xF800809C 0 2 0xF800C01C 1 0 0xF800C05C 1 1 0xF800C09C 1 2 Access Read...

Page 721: ...Register or WAVE 0 1 RA Compare has occurred since the last read of the Status Register if WAVE 1 CPBS RB Compare Status 0 RB Compare has not occurred since the last read of the Status Register or WAV...

Page 722: ...clock is disabled 1 clock is enabled MTIOA TIOA Mirror 0 TIOA is low If WAVE 0 this means that TIOA pin is low If WAVE 1 this means that TIOA is driven low 1 TIOA is high If WAVE 0 this means that TI...

Page 723: ...nables the Load Overrun Interrupt CPAS RA Compare 0 no effect 1 enables the RA Compare Interrupt CPBS RB Compare 0 no effect 1 enables the RB Compare Interrupt CPCS RC Compare 0 no effect 1 enables th...

Page 724: ...effect 1 disables the Load Overrun Interrupt if WAVE 0 CPAS RA Compare 0 no effect 1 disables the RA Compare Interrupt if WAVE 1 CPBS RB Compare 0 no effect 1 disables the RB Compare Interrupt if WAV...

Page 725: ...725 11054A ATARM 27 Jul 11 SAM9X25 725 11054A ATARM 27 Jul 11 SAM9X25 ETRGS External Trigger 0 no effect 1 disables the External Trigger Interrupt...

Page 726: ...A Compare Interrupt is disabled 1 the RA Compare Interrupt is enabled CPBS RB Compare 0 the RB Compare Interrupt is disabled 1 the RB Compare Interrupt is enabled CPCS RC Compare 0 the RC Compare Inte...

Page 727: ...ls can be synchronized to generate non overlapped waveforms All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty cy...

Page 728: ...waveform on one external I O line PWM Controller APB PWMx PWMx PWMx Channel Update Duty Cycle Counter PWM0 Channel PIO Interrupt Controller PMC MCK Clock Generator APB Interface Interrupt Generator C...

Page 729: ...ck in the Power Management Controller PMC before using the PWM However if the application does not require PWM operations the PWM clock can be stopped when not needed and be restarted later In this ca...

Page 730: ...the user interface registers 37 6 1 PWM Clock Generator Figure 37 2 Functional View of the Clock Generator Block Diagram Caution Before using the PWM macrocell the programmer must first enable the PWM...

Page 731: ...Channel Block Diagram Each of the 4 channels is composed of three blocks A clock selector which selects one of the clocks provided by the clock generator described in Section 37 6 1 PWM Clock Generato...

Page 732: ...both DIVA or DIVB divider the formula becomes respectively or the waveform duty cycle This channel parameter is defined in the CDTY field of the PWM_CDTYx register If the waveform is left aligned then...

Page 733: ...ounter increases up to CPRD and is reset This ends the period Thus for the same CPRD value the period for a center aligned channel is twice the period for a left aligned channel Waveforms are fixed at...

Page 734: ...RD PWM_CPRDx CDTY PWM_CDTYx PWM_CCNTx Output Waveform PWMx CPOL PWM_CMRx 0 Output Waveform PWMx CPOL PWM_CMRx 1 CHIDx PWM_ISR Left Aligned CPRD PWM_CPRDx CDTY PWM_CDTYx PWM_CCNTx Output Waveform PWMx...

Page 735: ...f writing simultaneously several CHIDx bits in the PWM_ENA register In such a situation all channels may have the same clock selector configuration and the same period specified 37 6 3 2 Source Clock...

Page 736: ...t status bit in PWM_ISR Regis ter according to the enabled channel s See Figure 37 7 The second method uses an Interrupt Service Routine associated with the PWM channel Note Reading the PWM_ISR regist...

Page 737: ...ister an interrupt is generated at the end of the corresponding channel period The interrupt remains active until a read operation in the PWM_ISR register occurs A channel interrupt is enabled by sett...

Page 738: ...nly 0 0x10 PWM Interrupt Enable Register PWM_IER Write only 0x14 PWM Interrupt Disable Register PWM_IDR Write only 0x18 PWM Interrupt Mask Register PWM_IMR Read only 0 0x1C PWM Interrupt Status Regist...

Page 739: ...k is turned off 1 CLK_DIV1 CLKA CLKB clock is clock selected by PREA PREB 2 255 CLKA CLKB clock is clock selected by PREA PREB divided by DIVA DIVB factor Value Name Description 0000 MCK Master Clock...

Page 740: ...WM output for channel x 37 7 3 PWM Disable Register Name PWM_DIS Address 0xF8034008 Access Write only CHIDx Channel ID 0 No effect 1 Disable PWM output for channel x 31 30 29 28 27 26 25 24 23 22 21 2...

Page 741: ...4 PWM Status Register Name PWM_SR Address 0xF803400C Access Read only CHIDx Channel ID 0 PWM output for channel x is disabled 1 PWM output for channel x is enabled 31 30 29 28 27 26 25 24 23 22 21 20...

Page 742: ...rrupt for PWM channel x 37 7 6 PWM Interrupt Disable Register Name PWM_IDR Address 0xF8034014 Access Write only CHIDx Channel ID 0 No effect 1 Disable interrupt for PWM channel x 31 30 29 28 27 26 25...

Page 743: ...nterrupt Mask Register Name PWM_IMR Address 0xF8034018 Access Read only CHIDx Channel ID 0 Interrupt for PWM channel x is disabled 1 Interrupt for PWM channel x is enabled 31 30 29 28 27 26 25 24 23 2...

Page 744: ...Dx Channel ID 0 No new channel period has been achieved since the last read of the PWM_ISR register 1 At least one new channel period has been achieved since the last read of the PWM_ISR register Note...

Page 745: ...The output waveform starts at a high level 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CPD CPOL CALG 7 6 5 4 3 2 1 0 CPRE Value Name Description 0000 MCK Master Clock 0001 M...

Page 746: ...X25 746 11054A ATARM 27 Jul 11 SAM9X25 CPD Channel Update Period 0 Writing to the PWM_CUPDx will modify the duty cycle at the next period start event 1 Writing to the PWM_CUPDx will modify the period...

Page 747: ...0 0xF8034224 1 0xF8034244 2 0xF8034264 3 Access Read write Only the first 16 bits internal channel counter size are significant CDTY Channel Duty Cycle Defines the waveform duty cycle This value must...

Page 748: ...or 1024 The resulting period formula will be By using a Master Clock divided by one of both DIVA or DIVB divider the formula becomes respectively or If the waveform is center aligned then the output w...

Page 749: ...0xF803426C 3 Access Read only CNT Channel Counter Register Internal counter value This register is reset when the channel is enabled writing CHIDx in the PWM_ENA register the counter reaches CPRD val...

Page 750: ...ed waveform when modify ing the waveform period or duty cycle Only the first 16 bits internal channel counter size are significant When CPD field of PWM_CMRx register 0 the duty cycle CDTY of PWM_CDTY...

Page 751: ...cies Below Table 38 1 lists the compatibility level of the Atmel Two wire Interface in Master Mode and a full I2C compatible device Note 1 START b000000001 Ack Sr 38 2 Embedded Characteristics 3 TWIs...

Page 752: ...k Diagram Figure 38 1 Block Diagram Table 38 2 Abbreviations Abbreviation Description TWI Two wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR An...

Page 753: ...th PIO lines To enable the TWI the programmer must perform the following step Program the PIO controller to dedicate TWD and TWCK as peripheral lines The user must not program TWD and TWCK as open dra...

Page 754: ...irst each byte must be followed by an acknowledgement The number of bytes per transfer is unlimited see Figure 38 4 Each transfer begins with a START condition and terminates with a STOP condition see...

Page 755: ...agram 38 8 3 Programming Master Mode The following registers have to be programmed before entering Master mode 1 DADR IADRSZ IADR if a 10 bit device is addressed The device address is used to access s...

Page 756: ...ed if enabled in the interrupt enable register TWI_IER If the slave acknowledges the byte the data written in the TWI_THR is then shifted in the internal shifter and transferred When an acknowledge is...

Page 757: ...rate the acknowledge The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte If an acknowledge is received the ma...

Page 758: ...ices 38 8 6 1 7 bit Slave Addressing When Addressing 7 bit slave devices the internal address bytes are used to perform random address read or write accesses to reach one or more data bytes within a m...

Page 759: ...d IADR 23 16 can be used the same as in 7 bit Slave Addressing Example Address a 10 bit device 10 bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 1 Program IADRSZ 1 2 Program DADR with 1 1 1 1 0...

Page 760: ...ter Mode Only The TWI interface can perform a Quick Command 1 Configure the master mode DADR CKDIV etc 2 Write the MREAD bit in the TWI_MMR register at the value of the one bit command to be sent 3 St...

Page 761: ...V CHDIV CKDIV in TWI_CWGR Needed only once Set the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address DADR Transfer direction bit Write bit MREAD 0 Load...

Page 762: ...d only once Set the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address DADR Internal address size IADRSZ Transfer direction bit Write bit MREAD 0 Load t...

Page 763: ...register Device slave address Internal address size if IADR used Transfer direction bit Write bit MREAD 0 Internal address size 0 Load Transmit register TWI_THR Data to send Read Status register TXRD...

Page 764: ...the Control register Master enable TWI_CR MSEN SVDIS Set the Master Mode register Device slave address Transfer direction bit Read bit MREAD 1 Start the transfer TWI_CR START STOP Read status register...

Page 765: ..._CR MSEN SVDIS Set the Master Mode register Device slave address Internal address size IADRSZ Transfer direction bit Read bit MREAD 1 Read Status register TXCOMP 1 END BEGIN Yes Set TWI clock CLDIV CH...

Page 766: ...ata to read but one Read status register TXCOMP 1 END Set the internal address TWI_IADR address Yes Yes Yes No Yes Read Receive Holding register TWI_RHR No Set the Control register Master enable TWI_C...

Page 767: ...mmer must reinitiate the data transfer If the user starts a transfer ex DADR START W Write in THR and if the bus is busy the TWI automatically waits for a STOP condition on the bus to initiate the tra...

Page 768: ...sent by the master START sent by the TWI DATA sent by the TWI Bus is busy Bus is free A transfer is programmed DADR W START Write THR Transfer is initiated TWI DATA transfer Transfer is kept Bus is c...

Page 769: ...atus Register RXRDY 0 Read TWI_RHR TXRDY 1 EOSACC 1 Write in TWI_THR Need to perform a master access Program the Master mode DADR SVDIS MSEN CLK R W Read Status Register ARBLST 1 MREAD 1 TXRDY 0 Write...

Page 770: ...or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR Slave ADdress field SVACC Slave ACCess flag is set and SVREAD Slave...

Page 771: ...e bit See Figure 38 28 on page 774 and Figure 38 29 on page 774 38 10 4 4 General Call In the case where a GENERAL CALL is performed GACC General Call ACCess flag is set After GACC is set it is up to...

Page 772: ...gister If a STOP condition or a REPEATED START an address different from SADR is detected SVACC is reset Figure 38 26 on page 772 describes the Write operation Figure 38 26 Write Access Ordered by a M...

Page 773: ...program ming bytes and the number of them The programming sequence has to be provided to the master 38 10 5 4 Clock Synchronization In both read and write modes it may happen that TWI_THR TWI_RHR buff...

Page 774: ...s read Figure 38 29 on page 774 describes the clock synchronization in Read mode Figure 38 29 Clock Synchronization in Write Mode DATA1 The clock is stretched after the ACK the state of TWD is undefin...

Page 775: ...t Reversal from Read to Write Mode 1 TXCOMP is only set at the end of the transmission because after the repeated start SADR is detected again Reversal of Write to Read The master initiates the commun...

Page 776: ...shown in Figure 38 32 on page 776 gives an example of read and write operations in Slave mode A polling or interrupt method can be used to check the status bits The interrupt method requires that the...

Page 777: ...777 11054A ATARM 27 Jul 11 SAM9X25 777 11054A ATARM 27 Jul 11 SAM9X25...

Page 778: ...de Register TWI_SMR Read write 0x00000000 0x0C Internal Address Register TWI_IADR Read write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read write 0x00000000 0x14 0x1C Reserved 0x20 St...

Page 779: ...te master read the START and STOP must both be set In multiple data bytes master read the STOP must be set after the last data received but one In master read mode if a NACK bit is received the STOP i...

Page 780: ...VDIS TWI Slave Mode Disabled 0 No effect 1 The slave mode is disabled The shifter and holding characters if it contains data are transmitted in case of read oper ation In write operation the character...

Page 781: ...ster write direction 1 Master read direction DADR Device Address The device address is used to access slave devices in read or write mode Those bits are only used in Master mode 31 30 29 28 27 26 25 2...

Page 782: ...s Read write Reset 0x00000000 SADR Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode SADR must be programmed before enabling...

Page 783: ...Internal Address Register Name TWI_IADR Address 0xF801000C 0 0xF801400C 1 0xF801800C 2 Access Read write Reset 0x00000000 IADR Internal Address 0 1 2 or 3 bytes depending on IADRSZ 31 30 29 28 27 26 2...

Page 784: ...00 TWI_CWGR is only used in Master mode CLDIV Clock Low Divider The SCL low period is defined as follows CHDIV Clock High Divider The SCL high period is defined as follows CKDIV Clock Divider The CKDI...

Page 785: ...er Ready automatically set reset 0 No character has been received since the last TWI_RHR read operation 1 A byte has been received in the TWI_RHR since the last read RXRDY behavior in Master mode can...

Page 786: ...reset This bit is only used in Slave mode 0 TWI is not addressed SVACC is automatically cleared after a NACK or a STOP condition is detected 1 Indicates that the address decoding sequence has matched...

Page 787: ...won 1 Arbitration lost Another master of the TWI bus has won the multi master arbitration TXCOMP is set at the same time SCLWS Clock Wait State automatically set reset This bit is only used in Slave...

Page 788: ...t Holding Register Ready Interrupt Enable SVACC Slave Access Interrupt Enable GACC General Call Access Interrupt Enable OVRE Overrun Error Interrupt Enable NACK Not Acknowledge Interrupt Enable ARBLST...

Page 789: ...olding Register Ready Interrupt Disable SVACC Slave Access Interrupt Disable GACC General Call Access Interrupt Disable OVRE Overrun Error Interrupt Disable NACK Not Acknowledge Interrupt Disable ARBL...

Page 790: ...gister Ready Interrupt Mask SVACC Slave Access Interrupt Mask GACC General Call Access Interrupt Mask OVRE Overrun Error Interrupt Mask NACK Not Acknowledge Interrupt Mask ARBLST Arbitration Lost Inte...

Page 791: ...38 11 10 TWI Receive Holding Register Name TWI_RHR Address 0xF8010030 0 0xF8014030 1 0xF8018030 2 Access Read only Reset 0x00000000 RXDATA Master or Slave Receive Holding Data 31 30 29 28 27 26 25 24...

Page 792: ...8 11 11 TWI Transmit Holding Register Name TWI_THR Address 0xF8010034 0 0xF8014034 1 0xF8018034 2 Access Read write Reset 0x00000000 TXDATA Master or Slave Transmit Holding Data 31 30 29 28 27 26 25 2...

Page 793: ...ntrol by automatic management of the pins RTS and CTS The USART supports the connection to the DMA Controller which enables data transfers to the transmitter and from the receiver The DMAC provides ch...

Page 794: ...ed with a data byte Automatic Identifier parity calculation sending and verification Parity sending and verification can be disabled Automatic Checksum calculation sending and verification Checksum se...

Page 795: ...able 39 1 SPI Operating Mode PIN USART SPI Slave SPI Master RXD RXD MOSI MISO TXD TXD MISO MOSI RTS RTS CS CTS CTS CS Peripheral DMA Controller Channel Channel Interrupt Controller Receiver USART Inte...

Page 796: ...4 Application Block Diagram Figure 39 2 Application Block Diagram Smart Card Slot USART RS485 Drivers Differential Bus IrDA Transceivers Field Bus Driver EMV Driver IrDA Driver IrLAP RS232 Drivers Ser...

Page 797: ...O TXD Transmit Serial Data or Master Out Slave In MOSI in SPI Master Mode or Master In Slave Out MISO in SPI Slave Mode I O RXD Receive Serial Data or Master In Slave Out MISO in SPI Master Mode or Ma...

Page 798: ...nt The USART is not continuously clocked The programmer must first enable the USART Clock in the Power Management Controller PMC before using the USART However if the application does not require USAR...

Page 799: ...connected on one of the internal sources of the Interrupt Controller Using the USART interrupt requires the Interrupt Controller to be programmed first Note that it is not recommended to use the USAR...

Page 800: ...munication RS485 with driver control signal ISO7816 T0 or T1 protocols for interfacing with smart cards NACK handling error counter with repetition and iteration limit InfraRed IrDA Modulation and Dem...

Page 801: ...AM9X25 Support both Classic and Enhanced checksum types Full LIN error checking and reporting Frame Slot Mode the Master allocates slots to the scheduled frames automatically Generation of the Wakeup...

Page 802: ...duration of the low and high levels of the signal pro vided on the SCK pin must be longer than a Master Clock MCK period The frequency of the signal provided on SCK must be at least 4 5 times lower th...

Page 803: ...edBaud Rate Calculation Result CD Actual Baud Rate Error MHz Bit s Bit s 3 686 400 38 400 6 00 6 38 400 00 0 00 4 915 200 38 400 8 00 8 38 400 00 0 00 5 000 000 38 400 8 14 8 39 062 50 1 70 7 372 800...

Page 804: ...e is only available when using USART normal mode The fractional Baud Rate is calculated using the following formula The modified architecture is presented below Figure 39 4 Fractional Baud Rate Genera...

Page 805: ...named FI as represented in Table 39 7 Table 39 8 shows the resulting Fi Di Ratio which is the ratio between the ISO7816 clock and the baud rate clock If the USART is configured in ISO7816 Mode the clo...

Page 806: ...ock is enabled After reset the transmitter is disabled The user must enable it by setting the TXEN bit in the Control Register US_CR However the transmitter registers can be programmed before being en...

Page 807: ...mber of stop bits is selected by the NBSTOP field in US_MR The 1 5 stop bit is sup ported in asynchronous mode only Figure 39 6 Character Transmit The characters are sent by writing in the Transmit Ho...

Page 808: ...r encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern Depending on the configuration the preamble is a training sequence composed of a...

Page 809: ...e second bit time Two distinct sync patterns are used the command sync and the data sync The command sync has a logic one level for one and a half bit times then a transition to logic zero for the sec...

Page 810: ...cycles after the expected edge then the current period is lengthened by one clock cycle These intervals are considered to be drift and so corrective actions are automatically taken Figure 39 11 Bit Re...

Page 811: ...ber of stop bits has no effect on the receiver as it considers only one stop bit regardless of the field NBSTOP so that resynchronization between the receiver and the transmitter can occur Moreover as...

Page 812: ...sition on incoming stream If RXD is sampled dur ing one quarter of a bit time to zero a start bit is detected See Figure 39 14 The sample pulse rejection mechanism applies Figure 39 14 Asynchronous St...

Page 813: ...ar mode the first bit of the frame has to be a zero to one transition 39 7 3 5 Radio Interface Manchester Encoded USART Application This section describes low data rate RF transmission systems and the...

Page 814: ...data When a logic 1 is sent the modulator out puts an RF signal at frequency F0 and switches to F1 if the data sent is a 0 See Figure 39 19 From the receiver side another carrier frequency is used The...

Page 815: ...eception in synchronous mode Figure 39 20 Synchronous Mode Character Reception 39 7 3 7 Receiver Operations When a character reception is completed it is transferred to the Receive Holding Register US...

Page 816: ...816 11054A ATARM 27 Jul 11 SAM9X25 Figure 39 21 Receiver Status D0 D1 D2 D3 D4 D5 D6 D7 RXD Start Bit Parity Bit Stop Bit Baud Rate Clock Write US_CR RXRDY OVRE D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Parit...

Page 817: ...k parity is used the parity generator of the transmitter drives the parity bit to 1 for all characters The receiver parity checker reports an error if the parity bit is sampled to 0 If the space parit...

Page 818: ...d SENDA is transmitted normally with the parity to 0 39 7 3 10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices The timeguard function enables the trans...

Page 819: ...iver Time out is disabled and no time out is detected The TIMEOUT bit in US_CSR remains to 0 Otherwise the receiver loads a 16 bit counter with the value programmed in TO This counter is decremented a...

Page 820: ...on RXD before the start of the frame does not provide a time out This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected If R...

Page 821: ...nsmitter holds the TXD line at least during one character until the user requests the break condition to be removed A break is transmitted by writing the Control Register US_CR with the STTBRK bit to...

Page 822: ...ng the TXD line for this period the transmitter resumes normal operations Figure 39 26 illustrates the effect of both the Start Break STTBRK and Stop Break STPBRK commands on the TXD line Figure 39 26...

Page 823: ...havior when Operating with Hardware Handshaking 39 7 4 ISO7816 Mode The USART features an ISO7816 compatible operating mode This mode permits interfacing with smart cards and Security Access Modules S...

Page 824: ...orm an exclusive OR on the data before writing it in the Transmit Holding Register US_THR or after reading it in the Receive Holding Register US_RHR 39 7 4 2 Protocol T 0 In T 0 protocol a character i...

Page 825: ...MAX_ITERATION does not equal zero the USART repeats the character as many times as the value loaded in MAX_ITERATION When the USART repetition number reaches MAX_ITERATION the ITERATION bit is set in...

Page 826: ...essible Note that the modulator and the demodulator are activated Figure 39 32 Connection to IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction o...

Page 827: ...pheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0 00 1 63 20 000 000 115 200 11 1 38 1 63 32 768 000 115 200 18 1 25 1 63 40 000 000 115 200 22 1 38 1 63 3 686 400 57 600 4 0...

Page 828: ...when the counter reaches 0 the input of the receiver is driven low during one bit time Figure 39 34 illustrates the operations of the IrDA demodulator Figure 39 34 IrDA Demodulator Operations As the...

Page 829: ...bus is shown in Figure 39 35 Figure 39 35 Typical Connection to a RS485 Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Regis ter US_MR to the value 0x1 The RTS pin...

Page 830: ...pplies the output data from the master shifted into the input of the slave Master In Slave Out MISO This data line supplies the output data from a slave to the input of the master Serial Clock SCK Thi...

Page 831: ...r the external clock SCK frequency must be at least 6 times lower than the system clock 39 7 7 3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling e...

Page 832: ...L 0 SCK CPOL 1 MOSI SPI Master TXD SPI Slave RXD NSS SPI Master RTS SPI Slave CTS SCK cycle for reference MSB MSB LSB LSB 6 6 5 5 4 4 3 3 2 2 1 1 1 2 3 4 5 7 8 6 MISO SPI Master RXD SPI Slave TXD SCK...

Page 833: ...de Chip Select Active After Transfer the slave select line NSS can be forced at low level by writing the Control Register US_CR with the RTSEN bit to 1 The slave select line NSS can be released at hig...

Page 834: ...The USART can act either as a LIN Master node or as a LIN Slave node The node configuration is chosen by setting the USART_MODE field in the USART Mode regis ter US_MR LIN Master Node USART_MODE 0xA L...

Page 835: ...and sent see Section 39 7 8 9 The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter As soon as the Synch Break Field is transmitted the flag LIN...

Page 836: ...eld character to be 0x55 This field is used to update the actual baud rate in order to stay synchronized see Section 39 7 8 8 If the received Synch character is not 0x55 an Inconsistent Synch Field er...

Page 837: ...nal part LINFP When the Synch Field has been received the clock divider CD and the fractional part FP are updated in the Baud Rate Generator register US_BRGR If it appears that the sampled Synch chara...

Page 838: ...dard imposes also that for communication between two nodes their bit rate must not differ by more than 2 This means that the Baudrate_deviation must not exceed 1 It follows from that a minimum value f...

Page 839: ...ssion the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register US_LINIR The bits 6 and 7 of this register are discarded During header r...

Page 840: ...e field Node Action NACT in the US_LINMR register see Section 39 8 16 Example a LIN cluster that contains a Master and two Slaves Data transfer from the Master to the Slave 1 and to the Slave 2 NACT M...

Page 841: ...eld of the LIN Mode register US_LINMR The response data length is equal to DLC 1 bytes DLC can be programmed from 0 to 255 so the response can contain from 1 data byte up to 256 data bytes DLM 1 the r...

Page 842: ...d the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2 0 slaves The USART can be configured to Send Check an Enhanced checksum automatically CHKDIS 0 C...

Page 843: ...ulated as below If the Checksum is sent CHKDIS 0 THeader_Nominal 34 x Tbit TResponse_Nominal 10 x NData 1 x Tbit TFrame_Maximum 1 4 x THeader_Nominal TResponse_Nominal 1 Note TFrame_Maximum 1 4 x 34 1...

Page 844: ...ong This flag can be set to 1 only if the checksum feature is enabled CHKDIS 0 This error is reported by flag LINCE in the Channel Status Register US_CSR Slave Not Responding Error This error is gener...

Page 845: ...have not been read redo the two previous steps Wait until LINTC in US_CSR rises Check the LIN errors Case 3 NACT IGNORE the USART is not concerned by the response Wait until LINTC in US_CSR rises Che...

Page 846: ...DLC in US_LINMR to configure the frame transfer IMPORTANT if the NACT configuration for this frame is PUBLISH the US_LINMR register must be write with NACT PUBLISH even if this field is already corre...

Page 847: ...Read RCHR in US_RHR If all the data have not been read redo the two previous steps Wait until LINTC in US_CSR rises Check the LIN errors Case 3 NACT IGNORE the USART is not concerned by the response...

Page 848: ...he on and off chip memories without any processor intervention The DMAC uses the trigger flags TXRDY and RXRDY to write or read into the USART The DMAC always writes in the Transmit Holding register U...

Page 849: ...second access the 8 bit DLC field is written PDCM 0 the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN Mode register US_LINMR The WRITE buffer also...

Page 850: ...ued by forcing the bus to the dominant state from 250 s to 5 ms For this it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits Whatever the baud rate is this charact...

Page 851: ...o sleep mode The time out delay period during which the receiver waits for a new character is programmed in the TO field of the Receiver Time out Register US_RTOR If the TO field is programmed to 0 th...

Page 852: ...eiver remains active Figure 39 55 Automatic Echo Mode Configuration 39 7 9 3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver as sho...

Page 853: ...gisters is detected then the WPVS flag in the USART Write Protect Status Register US_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is r...

Page 854: ...eiver Holding Register US_RHR Read only 0x0 0x001C Transmitter Holding Register US_THR Write only 0x0020 Baud Rate Generator Register US_BRGR Read write 0x0 0x0024 Receiver Time out Register US_RTOR R...

Page 855: ...Receiver Disable 0 No effect 1 Disables the receiver TXEN Transmitter Enable 0 No effect 1 Enables the transmitter if TXDIS is 0 TXDIS Transmitter Disable 0 No effect 1 Disables the transmitter RSTST...

Page 856: ...it TIMEOUT in US_CSR SENDA Send Address 0 No effect 1 In Multidrop Mode only the next character written to the US_THR is sent with the address bit set RSTIT Reset Iterations 0 No effect 1 Resets ITERA...

Page 857: ...lect Applicable if USART operates in SPI Master Mode USART_MODE 0xE RCS 0 No effect RCS 1 Releases the Slave Select Line NSS RTS pin LINABT Abort LIN Transmission 0 No effect 1 Abort the current LIN t...

Page 858: ...20 19 18 17 16 VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF CPOL 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE Value Name Description 0x0 NORMAL Normal mode 0x...

Page 859: ...lationship between master and slave devices PAR Parity Type NBSTOP Number of Stop Bits CHMODE Channel Mode Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits...

Page 860: ...ng Mode 0 16x Oversampling 1 8x Oversampling INACK Inhibit Non Acknowledge 0 The NACK is generated 1 The NACK is not generated DSNACK Disable Successive NACK 0 NACK is sent on the ISO line as soon as...

Page 861: ...er Decoder are disabled 1 Manchester Encoder Decoder are enabled MODSYNC Manchester Synchronization Mode 0 The Manchester Start bit is a 0 to 1 transition 1 The Manchester Start bit is a 1 to 0 transi...

Page 862: ...terrupt Enable ITER Max number of Repetitions Reached UNRE SPI Underrun Error NACK Non Acknowledge Interrupt Enable LINBK LIN Break Sent or LIN Break Received Interrupt Enable LINID LIN Identifier Sen...

Page 863: ...54A ATARM 27 Jul 11 SAM9X25 863 11054A ATARM 27 Jul 11 SAM9X25 LINIPE LIN Identifier Parity Interrupt Enable LINCE LIN Checksum Error Interrupt Enable LINSNRE LIN Slave Not Responding Error Interrupt...

Page 864: ...Disable ITER Max number of Repetitions Reached Disable UNRE SPI Underrun Error Disable NACK Non Acknowledge Interrupt Disable LINBK LIN Break Sent or LIN Break Received Interrupt Disable LINID LIN Ide...

Page 865: ...4A ATARM 27 Jul 11 SAM9X25 865 11054A ATARM 27 Jul 11 SAM9X25 LINIPE LIN Identifier Parity Interrupt Disable LINCE LIN Checksum Error Interrupt Disable LINSNRE LIN Slave Not Responding Error Interrupt...

Page 866: ...TY TXEMPTY Interrupt Mask ITER Max number of Repetitions Reached Mask UNRE SPI Underrun Error Mask NACK Non Acknowledge Interrupt Mask LINBK LIN Break Sent or LIN Break Received Interrupt Mask LINID L...

Page 867: ...11054A ATARM 27 Jul 11 SAM9X25 867 11054A ATARM 27 Jul 11 SAM9X25 LINIPE LIN Identifier Parity Interrupt Mask LINCE LIN Checksum Error Interrupt Mask LINSNRE LIN Slave Not Responding Error Interrupt M...

Page 868: ...received or End of Break detected since the last RSTSTA 1 Break Received or End of Break detected since the last RSTSTA OVRE Overrun Error 0 No overrun error has occurred since the last RSTSTA 1 At le...

Page 869: ...SART_MODE 0xA 0 No LIN Break has been sent since the last RSTSTA 1 At least one LIN Break has been sent since the last RSTSTA If USART operates in LIN Slave Mode USART_MODE 0xB 0 No LIN Break has rece...

Page 870: ...ch Field Error 0 No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA 1 The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected sinc...

Page 871: ...ss 0xF801C018 0 0xF8020018 1 0xF8024018 2 Access Read only RXCHR Received Character Last character received if RXRDY is set RXSYNH Received Sync 0 Last Character received is a Data 1 Last Character re...

Page 872: ...e Transmitted Next character to be transmitted after the current character if TXRDY is not set TXSYNH Sync Field to be transmitted 0 The next character sent is encoded as a data Start Frame Delimiter...

Page 873: ...n page 884 CD Clock Divider FP Fractional Part 0 Fractional divider is disabled 1 7 Baudrate resolution defined by FP x 1 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FP 15 14 13 12 11 10 9 8 CD...

Page 874: ...24 2 Access Read write This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 884 TO Time out Value 0 The Receiver Time out is disabled 1 131071 The...

Page 875: ...4028 2 Access Read write This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 884 TG Timeguard Value 0 The Transmitter Timeguard is disabled 1 255...

Page 876: ...can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 884 FI_DI_RATIO FI Over DI Ratio Value 0 If ISO7816 mode is selected the Baud Rate Generator generates no si...

Page 877: ...Name US_NER Address 0xF801C044 0 0xF8020044 1 0xF8024044 2 Access Read only NB_ERRORS Number of Errors Total number of errors that occurred during an ISO7816 transfer This register automatically clea...

Page 878: ...F801C04C 0 0xF802004C 1 0xF802404C 2 Access Read write This register can only be written if the WPEN bit is cleared in USART Write Protect Mode Register on page 884 IRDA_FILTER IrDA Filter Sets the fi...

Page 879: ...ero to one transition Logic One is coded as a one to zero transition 1 Logic Zero is coded as a one to zero transition Logic One is coded as a zero to one transition RX_PL Receiver Preamble Length 0 T...

Page 880: ...sition 1 Logic Zero is coded as a one to zero transition Logic One is coded as a zero to one transition DRIFT Drift compensation 0 The USART can not recover from an important clock drift 1 The USART c...

Page 881: ...utomatically In Slave node configuration the check sum is checked automatically 1 Whatever the node configuration is the checksum is not computed sent and it is not checked CHKTYP Checksum Type 0 LIN...

Page 882: ...ignal 1 setting the bit LINWKUP in the control register sends a LIN 1 3 wakeup signal DLC Data Length Control 0 255 Defines the response data length if DLM 0 in that case the response data length is e...

Page 883: ...or Read only IDCHR Identifier Character If USART_MODE 0xA Master node configuration IDCHR is Read write and its value is the Identifier character to be transmitted if USART_MODE 0xB Slave node configu...

Page 884: ...he registers USART Mode Register on page 858 USART Baud Rate Generator Register on page 873 USART Receiver Time out Register on page 874 USART Transmitter Timeguard Register on page 875 USART FI DI RA...

Page 885: ...Protect Violation has occurred since the last read of the US_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WP...

Page 886: ...886 11054A ATARM 27 Jul 11 SAM9X25 886 11054A ATARM 27 Jul 11 SAM9X25...

Page 887: ...e association with two DMA controller channels permits packet handling for these tasks with processor time reduced to a minimum 40 2 Embedded Characteristics Two pin UART Implemented Features are USAR...

Page 888: ...the Power Management Controller In this case the pro grammer must first configure the PMC to enable the UART clock Usually the peripheral identifier used for this purpose is 1 DMA Controller Baud Rate...

Page 889: ...the master clock divided by 16 times the value CD written in UART_BRGR Baud Rate Generator Register If UART_BRGR is set to 0 the baud rate clock is disabled and the UART remains inactive The maximum...

Page 890: ...bit period or shorter is ignored and the receiver continues to wait for a valid start bit When a valid start bit has been detected the receiver samples the URXD at the theoretical mid point of each bi...

Page 891: ...error bit PARE in UART_SR is set at the same time the RXRDY is set The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA Reset Status at 1 If a new character is r...

Page 892: ...ly stops the transmitter whether or not it is processing characters 40 5 3 2 Transmit Format The UART transmitter drives the pin UTXD at the baud rate clock speed The line is driven depending on the f...

Page 893: ...face 40 5 5 Test Modes The UART supports three test modes These modes of operation are programmed by using the field CHMODE Channel Mode in the mode register UART_MR The Automatic Echo mode allows bit...

Page 894: ...1054A ATARM 27 Jul 11 SAM9X25 Figure 40 11 Test Modes Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD VDD Disabled Receiver Transmitter Disabled RXD TXD Disabled Automatic...

Page 895: ...ode Register UART_MR Read write 0x0 0x0008 Interrupt Enable Register UART_IER Write only 0x000C Interrupt Disable Register UART_IDR Write only 0x0010 Interrupt Mask Register UART_IMR Read only 0x0 0x0...

Page 896: ...0 RXDIS Receiver Disable 0 No effect 1 The receiver is disabled If a character is being processed and RSTRX is not set the character is completed before the receiver is stopped TXEN Transmitter Enable...

Page 897: ...Channel Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE PAR 7 6 5 4 3 2 1 0 Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Space parity forced to...

Page 898: ...y RXRDY Enable RXRDY Interrupt TXRDY Enable TXRDY Interrupt OVRE Enable Overrun Error Interrupt FRAME Enable Framing Error Interrupt PARE Enable Parity Error Interrupt TXEMPTY Enable TXEMPTY Interrupt...

Page 899: ...XRDY Disable RXRDY Interrupt TXRDY Disable TXRDY Interrupt OVRE Disable Overrun Error Interrupt FRAME Disable Framing Error Interrupt PARE Disable Parity Error Interrupt TXEMPTY Disable TXEMPTY Interr...

Page 900: ...XRDY Interrupt TXRDY Disable TXRDY Interrupt OVRE Mask Overrun Error Interrupt FRAME Mask Framing Error Interrupt PARE Mask Parity Error Interrupt TXEMPTY Mask TXEMPTY Interrupt 0 The corresponding in...

Page 901: ...Shift Register OVRE Overrun Error 0 No overrun error has occurred since the last RSTSTA 1 At least one overrun error has occurred since the last RSTSTA FRAME Framing Error 0 No framing error has occur...

Page 902: ...9X25 40 6 7 UART Receiver Holding Register Name UART_RHR Address 0xF8040018 0 0xF8044018 1 Access Read only RXCHR Received Character Last received character if RXRDY is set 31 30 29 28 27 26 25 24 23...

Page 903: ...Holding Register Name UART_THR Address 0xF804001C 0 0xF804401C 1 Access Write only TXCHR Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set 3...

Page 904: ...40 6 9 UART Baud Rate Generator Register Name UART_BRGR Address 0xF8040020 0 0xF8044020 1 Access Read write CD Clock Divisor 0 Baud Rate Clock is disabled 1 to 65 535 MCK CD x 16 31 30 29 28 27 26 25...

Page 905: ...mailboxes can be enabled in the same time A priority can be defined for each mailbox independently An internal 16 bit timer is used to stamp each received and sent message This timer starts counting a...

Page 906: ...SAM9X25 41 3 Block Diagram Figure 41 1 CAN Block Diagram Internal Bus CAN Interrupt CANRX Controller Area Network PIO CANTX Error Counter User Interface PMC MCK Mailbox Priority Encoder MB0 MBx x num...

Page 907: ...n the Power Management Controller PMC before using the CAN A Low power Mode is defined for the CAN controller If the application does not require CAN operations the CAN clock can be stopped when not n...

Page 908: ...and V2 0 Part B It minimizes the CPU load in communication overhead The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself The CPU reads or writes d...

Page 909: ...0010010000100 1 11 01b ID6 101000100100010010000100 1 11 10b ID7 101000100100010010000100 1 11 11b The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values CAN_MIDx 001 1...

Page 910: ...ically sends the message with the highest priority first set with the field PRIOR in CAN_MMRx register It is also possible to configure a mailbox in Producer Mode In this mode when a remote frame is r...

Page 911: ...while TOVF is set In a CAN network some CAN devices may have a larger counter In this case the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a...

Page 912: ...he signal s propagation time on the bus line the input comparator delay and the output driver delay It is programmable to be 1 2 8 TQ long This parameter is defined in the PROPAG field of the CAN Baud...

Page 913: ...parameters BRP PROPAG PHASE1 and PHASE2 The time quantum is calculated as follows Note The BRP field must be within the range 1 0x7F i e BRP 0 is not authorized To compensate for phase shifts between...

Page 914: ...t be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1 We choose its maximum value Tsjw Min 4 Tcsc Tphs1 4 Tcsc SJW Tsjw Tcsc 1 3 Finally CAN_BR 0x00053255 CAN Bus Synchronization Two types...

Page 915: ...level during the bit stuffing area of a frame it generates an Error Frame starting with the next bit time Bit error BERR bit in CAN_SR register A bit error occurs if a transmitter sends a dominant bit...

Page 916: ...ode An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error An error passive unit cannot send an active error frame It takes part...

Page 917: ...ssion field Detection of a dominant bit in the last bit of EOF by a receiver or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter The C...

Page 918: ...gister Wait for SLEEP signal rising Now the CAN Controller clock can be disabled This is done by programming the Power Man agement Controller PMC Figure 41 8 Enabling Low power Mode 41 7 5 2 Disabling...

Page 919: ...be initialized with the CAN network parameters The CAN_BR register defines the sampling point in the bit time period CAN_BR must be set before the CAN controller is enabled by setting the CANEN field...

Page 920: ...CAN_IMR register The CAN_SR register gives all interrupt source states The following events may initiate one of the two interrupts Message object interrupt Data registers in the mailbox object are ava...

Page 921: ...pending messages in transmission have been sent Internal timer counter overflow interrupt This interrupt is generated when the internal timer rolls over Timestamp interrupt This interrupt is generated...

Page 922: ...sked depending on the mailbox flag in the CAN_IMR global register Message data are stored in the mailbox data register until the software application notifies that data processing has ended This is do...

Page 923: ...not belong to different messages the application must check the MMI field in the CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx If the MMI flag is set again after the data registers...

Page 924: ...mailbox and refused by previous ones see Figure 41 13 Figure 41 13 Chaining Three Mailboxes to Receive a Buffer Split into Three Messages If the number of mailboxes is not sufficient the MMI flag of...

Page 925: ...register It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field The answer to the remote frame is handled by another reception mailbox In this case the devic...

Page 926: ...are re tried automatically until they win the bus arbitration This feature can be disabled by setting the bit DRPT in the CAN_MR register In this case if the message was not sent the first time it was...

Page 927: ...r Producer Mode is enabled the MRDY flag in the CAN_MSR register is automatically set until the first transfer command The software application prepares data to be sent by writing to the CAN_MDHx and...

Page 928: ...pending for the mailbox while the MRDY flag is set This interrupt can be masked according to the mailbox flag in the CAN_IMR global register The MRTR bit in the CAN_MCRx register has no effect This f...

Page 929: ...setting the TTM bit in the CAN_MR register 41 8 4 1 Timestamping Mode Each mailbox has its own timestamp value Each time a message is sent or received by a mail box the 16 bit value MTIMESTAMP of the...

Page 930: ...in the 16 bit MTIMEMARK field of the CAN_MMRx register At each internal timer clock cycle the value of the CAN_TIM is compared with each mailbox time mark When the internal timer counter reaches the...

Page 931: ...last_mailbox_number CAN_TIM CAN BUS MRDY CAN_MSRx End of Frame Timer Event x MTIMEMARKx CAN_TIM Timer Event y MRDY CAN_MSRy MTIMEMARKy CAN_TIM Cleared by software Internal Counter Reset Message x Arbi...

Page 932: ...CAN_TIMESTP Read only 0x0 0x0020 Error Counter Register CAN_ECR Read only 0x0 0x0024 Transfer Command Register CAN_TCR Write only 0x0028 Abort Command Register CAN_ACR Write only 0x002C 0x01FC Reserve...

Page 933: ...each successful reception for mailboxes configured in Receive with without over write Mode Producer and Consumer TEOF Timestamp messages at each end of Frame 0 The value of CAN_TIM is captured in the...

Page 934: ...sable Repeat 0 When a transmit mailbox loses the bus arbitration the transfer request remains pending 1 When a transmit mailbox lose the bus arbitration the transfer request is automatically aborted I...

Page 935: ...t 1 Enable WARN interrupt ERRP Error Passive Mode Interrupt Enable 0 No effect 1 Enable ERRP interrupt BOFF Bus Off Mode Interrupt Enable 0 No effect 1 Enable BOFF interrupt SLEEP Sleep Interrupt Enab...

Page 936: ...e 0 No effect 1 Enable CRC Error interrupt SERR Stuffing Error Interrupt Enable 0 No effect 1 Enable Stuffing Error interrupt AERR Acknowledgment Error Interrupt Enable 0 No effect 1 Enable Acknowledg...

Page 937: ...ct 1 Disable WARN interrupt ERRP Error Passive Mode Interrupt Disable 0 No effect 1 Disable ERRP interrupt BOFF Bus Off Mode Interrupt Disable 0 No effect 1 Disable BOFF interrupt SLEEP Sleep Interrup...

Page 938: ...No effect 1 Disable CRC Error interrupt SERR Stuffing Error Interrupt Disable 0 No effect 1 Disable Stuffing Error interrupt AERR Acknowledgment Error Interrupt Disable 0 No effect 1 Disable Acknowle...

Page 939: ...upt is enabled ERRP Error Passive Mode Interrupt Mask 0 ERRP interrupt is disabled 1 ERRP interrupt is enabled BOFF Bus Off Mode Interrupt Mask 0 BOFF interrupt is disabled 1 BOFF interrupt is enabled...

Page 940: ...led SERR Stuffing Error Interrupt Mask 0 Bit Stuffing Error interrupt is disabled 1 Bit Stuffing Error interrupt is enabled AERR Acknowledgment Error Interrupt Mask 0 Acknowledgment Error interrupt is...

Page 941: ...the last read of CAN_SR 1 CAN controller Warning Limit has been reached since the last read of CAN_SR This flag is automatically cleared by reading CAN_SR register This flag is set depending on TEC an...

Page 942: ...k must be available when a WAKEUP event occurs This flag is automatically reset when the CAN Controller enters Low Power mode TOVF Timer Overflow 0 The timer has not rolled over FFFFh to 0000h 1 The t...

Page 943: ...nsfer 1 A bit error occurred during a previous transfer A bit error is set when the bit value monitored on the line is different from the bit value sent This flag is automatically cleared by reading C...

Page 944: ...e for phase shifts between clock oscillators of different controllers on bus The controller must re synchronize on any relevant signal edge of the current transmission The synchronization jump width d...

Page 945: ...0018 0 0xF8004018 1 Access Read only TIMERx Timer This field represents the internal CAN controller 16 bit timer value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TIMER15 TIM...

Page 946: ...ame When the value is captured the TSTP flag is set in the CAN_SR register If the TSTP mask in the CAN_IMR register is set an interrupt is generated while TSTP flag is set in the CAN_SR register This...

Page 947: ...s 0 it stays 0 and if it was greater than 127 then it is set to a value between 119 and 127 TEC Transmit Error Counter When a transmitter sends an ERROR FLAG TEC is increased by 8 except when the tran...

Page 948: ...have the same priority then the mailbox with the lowest number is sent first i e MB0 will be transferred before MB1 TIMRST Timer Reset Resets the internal timer counter If the internal timer counter...

Page 949: ...ield in the CAN_MCRx register for each mailbox 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 Mailbox Object Type Description Rec...

Page 950: ...first If several mailboxes have the same priority the mailbox with the lowest number is serviced first i e MBx0 is serviced before MBx 15 if they have the same priority MOT Mailbox Object Type This f...

Page 951: ...x is configured in reception but behaves as a Transmit Mailbox i e it sends a remote frame and waits for an answer 1 0 1 Producer Mailbox Mailbox is configured in transmission but also behaves like a...

Page 952: ...disable the mailbox before writing to CAN_MAMx registers MIDvB Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mai...

Page 953: ...ent access with the internal CAN core the application must disable the mailbox before writing to CAN_MIDx registers MIDvB Complementary bits for identifier in extended frame mode If MIDE is cleared MI...

Page 954: ...4C 1 2 0xF800426C 1 3 0xF800428C 1 4 0xF80042AC 1 5 0xF80042CC 1 6 0xF80042EC 1 7 Access Read only MFID Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx...

Page 955: ...f frame of the last message received or sent by the mailbox If the TEOF field in the CAN_MR register is set TIMESTAMP is the internal timer value at the end of frame of the last message received or se...

Page 956: ...er The remote frame transfer request has been aborted Producer The response to the remote frame transfer has been aborted Mailbox Object Type Description Receive At least one message has been received...

Page 957: ...data register Others have been ignored A mailbox with a lower priority may have accepted the message Receive with overwrite Set when at least two messages intended for the mailbox have been sent The...

Page 958: ...ication Otherwise the MDL value is locked by the CAN controller to send receive a new message In Receive with overwrite the CAN controller may modify MDL value while the software application reads MDH...

Page 959: ...ication Otherwise the MDH value is locked by the CAN controller to send receive a new message In Receive with overwrite the CAN controller may modify MDH value while the software application reads MDH...

Page 960: ...ect type in Consumer This requires only one mailbox It can also be handled using two mailboxes one in reception the other in transmission The MRTR and the MTCR bits must be set in the same time 31 30...

Page 961: ...Bx 15 if they have the same priority It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register Mailbox Object Type Description Receive No action Receive with...

Page 962: ...962 11054A ATARM 27 Jul 11 SAM9X25 962 11054A ATARM 27 Jul 11 SAM9X25...

Page 963: ...eep Mode and a conversion sequencer and connects with a DMA channel These features reduce both power consumption and processor intervention A whole set of reference voltages is generated internally fr...

Page 964: ...Name Description VDDANA Analog power supply ADVREF Reference voltage AD0 AD11 Analog input channels ADTRG External trigger ADCInterrupt ADTRG VDDANA ADVREF GND Trigger Selection Control Logic Successi...

Page 965: ...PIO Controller In this case the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function 42 5 5 Timer Triggers Timer Counters may or may not be used as hardware triggers d...

Page 966: ...register and of the LDATA field in the ADC_LCDR register read 0 42 6 4 Conversion Results When a conversion is completed the resulting 10 bit digital value is stored in the Channel Data Register ADC_...

Page 967: ...OVREx flag is set in the Overrun Status Register ADC_OVER Likewise new data converted when DRDY is high sets the GOVRE bit General Overrun Error in ADC_SR The OVREx flag is automatically cleared when...

Page 968: ...a conversion its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable EOC0 GOVRE CH0 ADC_CHSR ADC_SR ADC_SR Trigger event EOC1 CH1 ADC_CHSR ADC_SR OVRE0 ADC_OVER Undefi...

Page 969: ...sable ADC_CHDR Reg isters permit the analog channels to be enabled or disabled independently If the ADC is used with a DMA only the transfers of converted data from enabled channels are performed and...

Page 970: ...any combination of channels 0 up to 3 but no more i e in this case the sequence CH0 CH0 CH1 CH1 CH1 is impossible A sequence that repeats several times the same channel requires more enabled channels...

Page 971: ...6 10 Write Protection Registers To prevent any single software error that may corrupt ADC behavior certain address spaces can be write protected by setting the WPEN bit in the ADC Write Protect Mode...

Page 972: ...Converted Data Register ADC_LCDR Read only 0x00000000 0x24 Interrupt Enable Register ADC_IER Write only 0x28 Interrupt Disable Register ADC_IDR Write only 0x2C Interrupt Mask Register ADC_IMR Read on...

Page 973: ...Name ADC_CR Address 0xF804C000 Access Write only SWRST Software Reset 0 No effect 1 Resets the ADC simulating a hardware reset START Start Conversion 0 No effect 1 Begins analog to digital conversion...

Page 974: ...PRESCAL 7 6 5 4 3 2 1 0 Value Name Description 0 BITS_10 10 bit resolution 1 BITS_8 8 bit resolution Value Name Description 0 NORMAL Normal Mode The ADC Core and reference voltage circuitry are kept...

Page 975: ...DCClock 9 SUT576 576 periods of ADCClock 10 SUT640 640 periods of ADCClock 11 SUT704 704 periods of ADCClock 12 SUT768 768 periods of ADCClock 13 SUT832 832 periods of ADCClock 14 SUT896 896 periods o...

Page 976: ...to 11 So it is only possible to use the sequencer from CH0 to CH11 This register activates only if ADC_MR USEQ field is set to 1 Any USCHx field is taken into account only if ADC_CHSR CHx register fi...

Page 977: ...11 So it is only possible to use the sequencer from CH0 to CH11 This register activates only if ADC_MR USEQ field is set to 1 Any USCHx field is taken into account only if ADC_CHSR CHx register field...

Page 978: ...e WPEN bit is cleared in ADC Write Protect Mode Register on page 991 CHx Channel x Enable 0 No effect 1 Enables the corresponding channel Note if USEQ 1 in ADC_MR register CHx corresponds to the xth c...

Page 979: ...Register on page 991 CHx Channel x Disable 0 No effect 1 Disables the corresponding channel Warning If the corresponding channel is disabled during a conversion or if it is disabled then reenabled du...

Page 980: ...atus Register Name ADC_CHSR Address 0xF804C018 Access Read only CHx Channel x Status 0 Corresponding channel is disabled 1 Corresponding channel is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 981: ...The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new conver sion is completed CHNB Channel Number Indicates the last converted channel...

Page 982: ...of Conversion Interrupt Enable x DRDY Data Ready Interrupt Enable GOVRE General Overrun Error Interrupt Enable COMPE Comparison Event Interrupt Enable 0 No effect 1 Enables the corresponding interrupt...

Page 983: ...f Conversion Interrupt Disable x DRDY Data Ready Interrupt Disable GOVRE General Overrun Error Interrupt Disable COMPE Comparison Event Interrupt Disable 0 No effect 1 Disables the corresponding inter...

Page 984: ...Interrupt Mask x DRDY Data Ready Interrupt Mask GOVRE General Overrun Error Interrupt Mask COMPE Comparison Event Interrupt Mask 0 The corresponding interrupt is disabled 1 The corresponding interrup...

Page 985: ...o data has been converted since the last read of ADC_LCDR 1 At least one data has been converted and is available in ADC_LCDR GOVRE General Overrun Error 0 No General Overrun Error occurred since the...

Page 986: ...OVREx Overrun Error x 0 No overrun error on the corresponding channel since the last read of ADC_OVER 1 There has been an overrun error on the corresponding channel since the last read of ADC_OVER 31...

Page 987: ...L field is compared 1 All channels are compared TAG TAG of ADC_LDCR register 0 set CHNB to zero in ADC_LDCR 1 append the channel number to the conversion result in ADC_LDCR register 31 30 29 28 27 26...

Page 988: ...ritten if the WPEN bit is cleared in ADC Write Protect Mode Register on page 991 LOWTHRES Low Threshold Low threshold associated to compare settings of ADC_EMR register HIGHTHRES High Threshold High t...

Page 989: ...xF804C06C 0xF804C070 0xF804C074 0xF804C078 Access Read only DATA Converted Data The analog to digital conversion data is placed into this register at the end of a conversion and remains until a new co...

Page 990: ...trictly greater than the duration time of the longest con version sequence according to configuration of registers ADC_MR ADC_CHSR ADC_SEQR1 ADC_SEQR2 31 30 29 28 27 26 25 24 TRGPER 23 22 21 20 19 18...

Page 991: ...r on page 974 ADC Channel Sequence 1 Register on page 976 ADC Channel Sequence 2 Register on page 977 ADC Channel Enable Register on page 978 ADC Channel Disable Register on page 979 ADC Extended Mode...

Page 992: ...curred since the last read of the ADC_WPSR register If this violation is an unauthor ized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC Write Prot...

Page 993: ...a constant rate of 16 bits at 16 kHz The control channel is used to communicate with control registers of the HLSD at a maximum rate of 8 bits at 16 kHz The SMD performs all protocol related data con...

Page 994: ...on Worldwide compliance 43 3 Block Diagram Figure 43 1 Software Modem Device Block Diagram SMD Controller SMD Core AHB Wrapper AHB CPU Interrupt FIFO Interface 8x32 2 DMA Parallel Interface DIB Interf...

Page 995: ...detected on the Frame Sync signal The SSC s high level of programmability and its use of DMA permit a continuous high bit rate data transfer without processor intervention Featuring connection to DMA...

Page 996: ...ication Block Diagram Figure 44 2 Application Block Diagram SSC Interface PIO DMA APB Bridge MCK System Bus Peripheral Bus TF TK TD RF RK RD Interrupt Control SSC Interrupt PMC Interrupt Management Po...

Page 997: ...ly clocked The SSC interface may be clocked through the Power Management Controller PMC therefore the programmer must first configure the PMC to enable the SSC clock 44 6 3 Interrupt The SSC interface...

Page 998: ...be enabled disabled configuring the SSC Interrupt mask register Each pending and unmasked SSC interrupt will assert the SSC interrupt line The SSC interrupt ser vice routine can get the interrupt orig...

Page 999: ...is allows the SSC to support many slave mode data transfers The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2 Figure 44 3 SSC Functional Block Diagram 44 7 1 Clock...

Page 1000: ...aximal value is 4095 in the Clock Mode Register SSC_CMR allowing a Master Clock division by up to 8190 The Divided Clock is provided to both the Receiver and Transmitter When this field is programmed...

Page 1001: ...d to unpredict able results Figure 44 6 Transmitter Clock Management 44 7 1 3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external c...

Page 1002: ...be followed by synchronization data before data transmission The start event is configured by setting the Transmit Clock Mode Register SSC_TCMR See Start on page 1004 The frame synchronization is conf...

Page 1003: ...the shift register depending on the data format selected When the receiver shift register is full the SSC transfers this data in the holding register the sta tus flag RXRDY is set in SSC_SR and the da...

Page 1004: ...falling rising edge on TF RF On detection of a low level high level on TF RF On detection of a level change or an edge on TF RF A start can be programmed in the same manner on either side of the Trans...

Page 1005: ...LY STTDLY STTDLY STTDLY STTDLY STTDLY Start Falling Edge on TF Start Rising Edge on TF Start Low Level on TF Start High Level on TF Start Any Edge on TF Start Level Change on TF X RK RF Input RD Input...

Page 1006: ...ter can transfer Transmit Sync Holding Register in the Shifter Register The data length to be sampled shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR SSC_TFMR and...

Page 1007: ...urs This selection is done with the bit STOP in SSC_RCMR 44 7 7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Registe...

Page 1008: ...LEN Up to 16 Size of Synchro data register SSC_TFMR DATDEF 0 or 1 Data default value ended SSC_TFMR FSDEN Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up...

Page 1009: ...Most bits in SSC_SR have a corresponding bit in interrupt management registers The SSC can be programmed to generate an interrupt when it detects an event The interrupt is controlled by writing SSC_IE...

Page 1010: ...lications supported by the SSC are not listed here Figure 44 17 Audio Application Block Diagram Figure 44 18 Codec Application Block Diagram SSC RK RF RD TD TF TK Clock SCK Word Select WS Data SD I2S...

Page 1011: ...M9X25 Figure 44 19 Time Slot Application Block Diagram SSC RK RF RD TD TF TK SCLK FSYNC Data Out Data in CODEC First Time Slot Serial Data Clock SCLK Frame sync FSYNC Serial Data Out Serial Data in CO...

Page 1012: ...ite Pro tect Status Register US_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted The WPVS flag is reset by writing the SSC Write Protect Mode Register S...

Page 1013: ...te 0x0 0x20 Receive Holding Register SSC_RHR Read only 0x0 0x24 Transmit Holding Register SSC_THR Write only 0x28 Reserved 0x2C Reserved 0x30 Receive Sync Holding Register SSC_RSHR Read only 0x0 0x34...

Page 1014: ...being received disables at end of current character reception TXEN Transmit Enable 0 No effect 1 Enables Transmit if TXDIS is not set TXDIS Transmit Disable 0 No effect 1 Disables Transmit If a charac...

Page 1015: ...be written if the WPEN bit is cleared in SSC Write Protect Mode Register DIV Clock Divider 0 The Clock Divider is not active Any Other Value The Divided Clock equals the Master Clock divided by 2 time...

Page 1016: ...output is shifted out on Receive Clock rising edge 1 The data inputs Data and Frame Sync signals are sampled on Receive Clock rising edge The Frame Sync signal out put is shifted out on Receive Clock...

Page 1017: ...relation to TAG Receive Sync Data reception PERIOD Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal...

Page 1018: ...he data register is sampled first in the bit stream DATNB Data Number per Frame This field defines the number of data words to be received after each transfer start which is equal to DATNB 1 FSLEN Rec...

Page 1019: ...ension Extends FSLEN field For details refer to FSLEN bit description on page 1018 Value Name Description RF Pin 0 NONE None Input only 1 NEGATIVE Negative Pulse Output 2 POSITIVE Positive Pulse Outpu...

Page 1020: ...signal input is sampled on Transmit clock rising edge 1 The data outputs Data and Frame Sync signals are shifted out on Transmit Clock rising edge The Frame sync signal input is sampled on Transmit c...

Page 1021: ...selected Transmit Clock to generate a new Frame Sync Signal If 0 no period signal is generated If not 0 a period signal is generated at each 2 x PERIOD 1 Transmit Clock Value Name Description 0 NONE N...

Page 1022: ...The lowest significant bit of the data register is shifted out first in the bit stream 1 The most significant bit of the data register is shifted out first in the bit stream DATNB Data Number per fram...

Page 1023: ...ch edge on frame sync will generate the interrupt TXSYN Status Register FSLEN_EXT FSLEN Field Extension Extends FSLEN field For details refer to FSLEN bit description on page 1022 Value Name Descripti...

Page 1024: ...efined by DATLEN in SSC_RFMR 44 9 8 SSC Transmit Holding Register Name SSC_THR Address 0xF0010024 Access Write only TDAT Transmit Data Right aligned regardless of the number of data bits defined by DA...

Page 1025: ...27 Jul 11 SAM9X25 44 9 9 SSC Receive Synchronization Holding Register Name SSC_RSHR Address 0xF0010030 Access Read only RSDAT Receive Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 1026: ...7 Jul 11 SAM9X25 44 9 10 SSC Transmit Synchronization Holding Register Name SSC_TSHR Address 0xF0010034 Access Read write TSDAT Transmit Synchronization Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 1027: ...ve Compare 0 Register Name SSC_RC0R Address 0xF0010038 Access Read write This register can only be written if the WPEN bit is cleared in SSC Write Protect Mode Register CP0 Receive Compare Data 0 31 3...

Page 1028: ...ve Compare 1 Register Name SSC_RC1R Address 0xF001003C Access Read write This register can only be written if the WPEN bit is cleared in SSC Write Protect Mode Register CP1 Receive Compare Data 1 31 3...

Page 1029: ...while previous data has not been read since the last read of the Status Register 1 Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register...

Page 1030: ...eive Sync 0 An Rx Sync has not occurred since the last read of the Status Register 1 An Rx Sync has occurred since the last read of the Status Register TXEN Transmit Enable 0 Transmit is disabled 1 Tr...

Page 1031: ...0 No effect 1 Enables the Receive Ready Interrupt OVRUN Receive Overrun Interrupt Enable 0 No effect 1 Enables the Receive Overrun Interrupt CP0 Compare 0 Interrupt Enable 0 No effect 1 Enables the C...

Page 1032: ...No effect 1 Disables the Receive Ready Interrupt OVRUN Receive Overrun Interrupt Disable 0 No effect 1 Disables the Receive Overrun Interrupt CP0 Compare 0 Interrupt Disable 0 No effect 1 Disables th...

Page 1033: ...Ready Interrupt is enabled OVRUN Receive Overrun Interrupt Mask 0 The Receive Overrun Interrupt is disabled 1 The Receive Overrun Interrupt is enabled CP0 Compare 0 Interrupt Mask 0 The Compare 0 Int...

Page 1034: ...Clock Mode Register on page 1015 SSC Receive Clock Mode Register on page 1016 SSC Receive Frame Mode Register on page 1018 SSC Transmit Clock Mode Register on page 1020 SSC Transmit Frame Mode Regist...

Page 1035: ...ion has occurred since the last read of the SSC_WPSR register If this violation is an unauthorized attempt to write a protected register the associated violation is reported into field WPVSRC WPVSRC W...

Page 1036: ...1036 11054A ATARM 27 Jul 11 SAM9X25 1036 11054A ATARM 27 Jul 11 SAM9X25...

Page 1037: ...compatible with IEEE 802 3 45 2 Embedded Characteristics Supports MII Interface to the physical layer Compatible with IEEE Standard 802 3 10 and 100 Mbit s Operation Full and Half duplex Operation Sta...

Page 1038: ...ATARM 27 Jul 11 SAM9X25 45 3 Block Diagram Figure 45 1 EMAC Block Diagram APB Slave Register Interface DMA Interface Address Checker Statistics Registers Control Registers Ethernet Receive Ethernet Tr...

Page 1039: ...al memory through its AHB bus interface It contains receive and transmit FIFOs for buffering frame data It loads the transmit FIFO and empties the receive FIFO using AHB bus master operations Receive...

Page 1040: ...ster The receive buffer start location is a word address For the first buffer of a frame the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the n...

Page 1041: ...ointer value which is the queue entry currently being accessed The counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descripto...

Page 1042: ...it zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received the frame is discarded and the receive resource error statistics register is incre...

Page 1043: ...twork control register Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register Rewriting the start bit while transmission is acti...

Page 1044: ...the number of collisions seen After the first collision 1 bit is used after the second 2 and so on up to 10 Above 10 all 10 bits are used An error is indicated and no further attempts are made if 16...

Page 1045: ...gister The pause time register decrements every 512 bit times i e 128 rx_clks in nibble mode once transmission has stopped For test purposes the register decrements every rx_clk cycle once transmissio...

Page 1046: ...he destination address The first bit of the destination address the LSB of the first byte of the frame is the group individual bit this is One for multicast addresses and Zero for unicast The All Ones...

Page 1047: ...4 bit hash register using the following hash function The hash function is an exclusive or of every sixth bit of the destination address hash_index 5 da 5 da 11 da 17 da 23 da 29 da 35 da 41 da 47 has...

Page 1048: ...out VLAN tagged frames Bit 21 set if receive frame is VLAN tagged i e type id of 0x8100 Bit 20 set if receive frame is priority tagged i e type id of 0x8100 and null VID If bit 20 is set bit 21 is set...

Page 1049: ...bits for transmit ETX0 and ETX1 and two bits for receive ERX0 and ERX1 There is a Transmit Enable ETXEN a Receive Error ERXER a Carrier Sense ECRS_DV and a 50 MHz Reference Clock ETXCK_EREFCK for 100...

Page 1050: ...ry These buffers are listed in another data structure that also resides in main memory This data structure receive buffer queue is a sequence of descriptor entries as defined in Receive Buffer Descrip...

Page 1051: ...hen the top register is written See Address Checking Block on page 1046 for details of address matching Each reg ister pair may be written at any time regardless of whether the receive circuits are en...

Page 1052: ...ddress in system memory to write the frame to Once the frame has been completely and successfully received and written to system memory the EMAC then updates the receive buffer descriptor entry with t...

Page 1053: ...tted Ok Register EMAC_FTO Read write 0x0000_0000 0x44 Single Collision Frames Register EMAC_SCF Read write 0x0000_0000 0x48 Multiple Collision Frames Register EMAC_MCF Read write 0x0000_0000 0x4C Fram...

Page 1054: ...A2B Read write 0x0000_0000 0xA4 Specific Address 2 Top Register EMAC_SA2T Read write 0x0000_0000 0xA8 Specific Address 3 Bottom Register EMAC_SA3B Read write 0x0000_0000 0xAC Specific Address 3 Top Re...

Page 1055: ...es the Ethernet transmitter to send data When reset transmission stops immediately the transmit FIFO and control registers are cleared and the transmit queue pointer register resets to point to the st...

Page 1056: ...1 SAM9X25 1056 11054A ATARM 27 Jul 11 SAM9X25 TSTART Start transmission Writing one to this bit starts transmission THALT Transmit halt Writing one to this bit halts transmission as soon as any ongoin...

Page 1057: ...bytes to be accepted NBC No Broadcast When set to 1 frames addressed to the broadcast address of all ones are not received MTI Multicast Hash Enable When set multicast frames are received when the 6...

Page 1058: ...f the first receive buffer RLCE Receive Length field Checking Enable When set frames with measured lengths shorter than their length fields are discarded Frames containing a type ID in bytes 13 and 14...

Page 1059: ...F802C008 Access Read only MDIO Returns status of the mdio_in pin Use the PHY maintenance register for reading managed frames rather than this bit IDLE 0 The PHY logic is running 1 The PHY management l...

Page 1060: ...ared by writing a one to this bit TGO Transmit Go If high transmit is active BEX Buffers exhausted mid frame If the buffers run out during transmission of a frame then transmission stops FCS shall be...

Page 1061: ...value increments as buffers are used Software should not use this register for determining where to remove received frames from the queue as it con stantly changes as new frames are received Software...

Page 1062: ...4 buffers or when the wrap bit of the entry is set This register can only be written when bit 3 in the transmit status register is low As transmit buffer reads consist of bursts of two words it is rec...

Page 1063: ...e pointer each time a new frame starts until a valid pointer is found This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared Cleared by w...

Page 1064: ...hernet Transmit Buffer Underrun The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK Also set if a used bit is read mid frame or when a new transmit queu...

Page 1065: ...1 SAM9X25 1065 11054A ATARM 27 Jul 11 SAM9X25 PFRE Pause Frame Received Indicates a valid pause has been received Cleared on a read PTZ Pause Time Zero Set when the pause time register 0x38 decrements...

Page 1066: ...it read interrupt TUND Ethernet Transmit Buffer Underrun Enable transmit underrun interrupt RLE Retry Limit Exceeded Enable retry limit exceeded interrupt TXERR Enable transmit buffers exhausted in mi...

Page 1067: ...1067 11054A ATARM 27 Jul 11 SAM9X25 1067 11054A ATARM 27 Jul 11 SAM9X25 PTZ Pause Time Zero Enable pause time zero interrupt...

Page 1068: ...t read interrupt TUND Ethernet Transmit Buffer Underrun Disable transmit underrun interrupt RLE Retry Limit Exceeded Disable retry limit exceeded interrupt TXERR Disable transmit buffers exhausted in...

Page 1069: ...1069 11054A ATARM 27 Jul 11 SAM9X25 1069 11054A ATARM 27 Jul 11 SAM9X25 PTZ Pause Time Zero Disable pause time zero interrupt...

Page 1070: ...interrupt masked TUND Ethernet Transmit Buffer Underrun Transmit underrun interrupt masked RLE Retry Limit Exceeded Retry limit exceeded interrupt masked TXERR Transmit buffers exhausted in mid frame...

Page 1071: ...1071 11054A ATARM 27 Jul 11 SAM9X25 1071 11054A ATARM 27 Jul 11 SAM9X25 PTZ Pause Time Zero Pause time zero interrupt masked...

Page 1072: ...ad operation this contains the data read from the PHY CODE Must be written to 10 Reads as written REGA Register Address Specifies the register in the PHY to access PHYA PHY Address RW Read write 10 is...

Page 1073: ...Pause Time Register Name EMAC_PTR Address 0xF802C038 Access Read write PTIME Pause Time Stores the current value of the pause time register which is decremented every 512 bit times 31 30 29 28 27 26...

Page 1074: ...e Hash Addressing on page 1047 45 6 15 Hash Register Top Name EMAC_HRT Address 0xF802C094 Access Read write ADDR Bits 63 32 of the hash address register See Hash Addressing on page 1047 31 30 29 28 27...

Page 1075: ...lticast or unicast and corre sponds to the least significant bit of the first byte received 45 6 17 Specific Address 1 Top Register Name EMAC_SA1T Address 0xF802C09C Access Read write ADDR The most si...

Page 1076: ...lticast or unicast and corre sponds to the least significant bit of the first byte received 45 6 19 Specific Address 2 Top Register Name EMAC_SA2T Address 0xF802C0A4 Access Read write ADDR The most si...

Page 1077: ...lticast or unicast and corre sponds to the least significant bit of the first byte received 45 6 21 Specific Address 3 Top Register Name EMAC_SA3T Address 0xF802C0AC Access Read write ADDR The most si...

Page 1078: ...lticast or unicast and corre sponds to the least significant bit of the first byte received 45 6 23 Specific Address 4 Top Register Name EMAC_SA4T Address 0xF802C0B4 Access Read write ADDR The most si...

Page 1079: ...X25 45 6 24 Type ID Checking Register Name EMAC_TID Address 0xF802C0B8 Access Read write TID Type ID checking For use in comparisons with received frames TypeID Length field 31 30 29 28 27 26 25 24 23...

Page 1080: ...rite RMII Reduce MII When set this bit enables the RMII operation mode When reset it selects the MII mode CLKEN Clock Enable When set this bit enables the transceiver input clock Setting this bit to 0...

Page 1081: ...Frames Received Register Name EMAC_PFR Address 0xF802C03C Access Read write FROK Pause Frames received OK A 16 bit register counting the number of good pause frames received A good frame has a length...

Page 1082: ...mitted i e no underrun 45 6 26 4 Multicollision Frames Register Name EMAC_MCF Address 0xF802C048 Access Read write MCF Multicollision Frames A 16 bit register counting the number of frames experiencin...

Page 1083: ...rrors 45 6 26 6 Frames Check Sequence Errors Register Name EMAC_FCSE Address 0xF802C050 Access Read write FCSE Frame Check Sequence Errors An 8 bit register counting frames that are an integral number...

Page 1084: ...if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes 45 6 26 8 Deferred Transmission Frames Register Name EMAC_DTF Address 0xF802C058 Access Re...

Page 1085: ...late collision is counted twice i e both as a collision and a late collision 45 6 26 10 Excessive Collisions Register Name EMAC_ECOL Address 0xF802C060 Access Read write EXCOL Excessive Collisions An...

Page 1086: ...Read write CSE Carrier Sense Errors An 8 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being...

Page 1087: ...ied to memory because no receive buffer was available 45 6 26 14 Receive Overrun Errors Register Name EMAC_ROV Address 0xF802C070 Access Read write ROVR Receive Overrun An 8 bit register counting the...

Page 1088: ...t in the network configuration register If the frame is larger it is recorded as a jabber error 45 6 26 16 Excessive Length Errors Register Name EMAC_ELE Address 0xF802C078 Access Read write EXL Exces...

Page 1089: ...have either a CRC error an alignment error or a receive symbol error 45 6 26 18 Undersize Frames Register Name EMAC_USF Address 0xF802C080 Access Read write USF Undersize frames An 8 bit register coun...

Page 1090: ...ress 0xF802C088 Access Read write RLFM Receive Length Field Mismatch An 8 bit register counting the number of frames received that have a measured length shorter than that extracted from its length fi...

Page 1091: ...ct device reli ability Junction Temperature 125 C Storage Temperature 60 C to 150 C Voltage on Input Pins with Respect to Ground 0 3V to VDDIO 0 3V 4V max Maximum Operating Voltage VDDCORE VDDPLLA VDD...

Page 1092: ...O 0 4 V CMOS IO 0 3 mA VVDDIO from 1 65V to 1 95V VVDDIO 0 1 V TTL IO Max VVDDIO from 1 65V to 1 95V VVDDIO 0 4 V VT Schmitt trigger Negative going threshold Voltage IO Max VVDDIO from 3 0V to 3 6V 0...

Page 1093: ...wer Consumption versus Modes The values in Table 46 3 and Table 46 4 on page 1094 are estimated values of the power con sumption with operating conditions as follows VDDIOM 1 8V VDDIOP0 and 1 3 3V VDD...

Page 1094: ...it Active ARM Core clock is 400 MHz MCK is 133 MHz All peripheral clocks activated onto AMP2 109 mA Idle Idle state waiting an interrupt All peripheral clocks de activated onto AMP2 38 mA Ultra low po...

Page 1095: ...4 pF 13 5 pF which means that 27 pF is the target value 27 pF from xin to gnd and 27 pF from xout to gnd If 20 pF load is targeted the sum of pad package board and external capacitances must be 20 pF...

Page 1096: ...Generator Main Oscillator Register in the PMC section 1K XIN XOUT GNDPLL CLEXT CLEXT CCRYSTAL Table 46 8 Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resi...

Page 1097: ...Hz Duty Duty Cycle 45 50 55 IDD ON Power Consumption Oscillation 86 86 140 125 A tON Startup time 6 10 s IDD STDBY Standby consumption 22 A Table 46 11 32 kHz Oscillator Characteristics Symbol Paramet...

Page 1098: ...768 kHz 0 6 2 pF IDD ON Current dissipation RS 50 k 1 CCRYSTAL32 6 pF 0 55 1 3 A RS 50 k 1 CCRYSTAL32 12 5pF 0 85 1 6 A RS 100 k 1 CCRYSTAL32 6 pF 0 7 2 0 A RS 100 k 1 CCRYSTAL32 12 5 pF 1 1 2 2 A ID...

Page 1099: ...cle 45 55 tST Startup Time 75 s IDD ON Power Consumption Oscillation After startup time 1 1 2 1 A IDD STDBY Standby consumption 0 4 A Table 46 15 PLLA Characteristics Symbol Parameter Conditions Min T...

Page 1100: ...p Characteristics Symbol Parameter Conditions Min Typ Max Unit FIN Input Frequency 4 12 32 MHz FOUT Output Frequency 450 480 600 MHz IPLL Current Consumption active mode 5 8 mA standby mode 1 5 A T St...

Page 1101: ...umption 8 A LS FS Transceiver and I O current consumption no connection 1 3 A IVDDUTMIC Core PLL and Oscillator current consumption 2 A Table 46 21 Dynamic Power Consumption Symbol Parameter Condition...

Page 1102: ...Table 46 22 Channel Conversion Time and ADC Clock Parameter Conditions Min Typ Max Units ADC Clock Frequency 10 bit resolution mode 13 2 MHz Startup Time Return from Idle Mode 40 s Track and Hold Acq...

Page 1103: ...the device from booting Table 46 25 Transfer Characteristics Parameter Min Typ Max Units Resolution 10 bit Integral Non linearity 2 LSB Differential Non linearity ADC Clock 13 2 MHz ADC Clock 5 MHz 2...

Page 1104: ...able 46 2 for more details Tres T1 T2 at the latest after VDDCORE has reached Vth TRES is a POR characteristic T1 3 x TSLCK T2 16 x TSLCK The TSLCK min 22 s is obtained for the maximum frequency of th...

Page 1105: ...the following tables tCPMCK is MCK period 46 14 2 Timing Extraction 46 14 2 1 Zero Hold Mode Restrictions Table 46 26 Capacitance Load Corner Supply MAX MIN 3 3V 50pF 5 pF 1 8V 30 pF 5 pF Table 46 27...

Page 1106: ...K 4 3 nrd setup nrd pulse ncs rd setup tCPMCK 4 4 ns SMC7 NRD Pulse Width nrd pulse tCPMCK 3 2 nrd pulse tCPMCK 3 3 ns Table 46 29 SMC Read Signals NCS Controlled READ_MODE 0 Symbol Parameter Min Unit...

Page 1107: ...lse Width nwe pulse tCPMCK 3 2 nwe pulse tCPMCK 3 2 ns SMC17 NBS0 A0 NBS1 NBS2 A1 NBS3 A2 A25 valid before NWE low nwe setup tCPMCK 4 2 nwe setup tCPMCK 4 0 ns SMC18 NCS low before NWE high nwe setup...

Page 1108: ...lid before NCS low ncs wr setup tCPMCK 3 6 ncs wr setup tCPMCK 3 5 ns SMC25 NWE low before NCS high ncs wr setup nwe setup ncs pulse tCPMCK 4 6 ncs wr setup nwe setup ncs pulse tCPMCK 4 6 ns SMC26 NCS...

Page 1109: ...equency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes Master Write Mode The SPI is only sending data to a slave device such as an L...

Page 1110: ...ead mode is given by SPCK pad Slave Write Mode Tsetup is the setup time from the master before sampling data 12ns This gives FSPCKMax 39 MHz VDDIO 3 3V 46 16 1 2 Timing Conditions Timings are given as...

Page 1111: ...A ATARM 27 Jul 11 SAM9X25 1111 11054A ATARM 27 Jul 11 SAM9X25 Figure 46 6 SPI Master mode 0 and 3 Figure 46 7 SPI Slave mode 0 and 3 SPCK MISO MOSI SPI5 SPI3 SPI4 SPCK MISO MOSI SPI6 SPI7 SPI8 NPCS0 S...

Page 1112: ...6 SPI12 SPI15 SPI13 SPCK CPOL 1 SPI6 SPI9 Table 46 33 SPI Timings with 3 3V Peripheral Supply Symbol Parameter Cond Min Max Units Master Mode SPISPCK SPI Clock 66 MHz SPI0 MISO Setup time before SPCK...

Page 1113: ...6 34 SPI Timings with 1 8V Peripheral Supply Symbol Parameter Cond Min Max Units Master Mode SPISPCK SPI Clock 66 MHz SPI0 MISO Setup time before SPCK rises 15 9 ns SPI1 MISO Hold time after SPCK rise...

Page 1114: ...46 16 2 SSC 46 16 2 1 Timing conditions Timings are given assuming a capacitance load on Table 46 35 46 16 2 2 Timing Extraction Figure 46 11 SSC Transmitter TK and TF in output SPCK MISO MOSI SPI2ma...

Page 1115: ...Figure 46 12 SSC Transmitter TK in input and TF in output Figure 46 13 SSC Transmitter TK in output and TF in input Figure 46 14 SSC Transmitter TK and TF in input TK CKI 1 TF TD SSC1 TK CKI 0 TK CKI...

Page 1116: ...9X25 Figure 46 15 SSC Receiver RK and RF in input Figure 46 16 SSC Receiver RK in input and RF in output Figure 46 17 SSC Receiver RK and RF in output RK CKI 1 RF RD SSC8 SSC9 RK CKI 0 RK CKI 0 RD SSC...

Page 1117: ...TK output 1 8V domain 3 3 3V domain 4 0 0 ns SSC4 1 TK edge to TD TK output TF input 1 8V domain 3 3 3V domain 4 5 6 2 tCPMCK 1 4 4 6 2 tCPMCK 1 4 5 7 2 tCPMCK 1 4 4 7 2 tCPMCK 1 4 ns SSC5 TF setup t...

Page 1118: ...0pF 4 3 3V domain VVDDIO from 3 0V to 3 6V maximum external capacitor 30pF Figure 46 19 Min and Max access time of output signals 46 16 3 HSMCI The High Speed MultiMedia Card Interface HSMCI supports...

Page 1119: ...mbol Parameter Min ns Max ns EMAC1 Setup for EMDIO from EMDC rising 10 ns EMAC2 Hold for EMDIO from EMDC rising 10 ns EMAC3 EMDIO toggling from EMDC rising 0 ns 1 300 ns 1 EMDC EMDIO EMAC3 max EMAC1 E...

Page 1120: ...11054A ATARM 27 Jul 11 SAM9X25 Figure 46 21 EMAC MII Mode Signals EMDC EMDIO ECOL ECRS ETXCK ETXER ETXEN ETX 3 0 ERXCK ERX 3 0 ERXER ERXDV EMAC3 EMAC1 EMAC2 EMAC4 EMAC5 EMAC6 EMAC7 EMAC8 EMAC9 EMAC10...

Page 1121: ...x ns EMAC21 ETXEN toggling from EREFCK rising 2 1 16 1 EMAC22 ETX toggling from EREFCK rising 2 1 16 1 EMAC23 Setup for ERX from EREFCK rising 4 EMAC24 Hold for ERX from EREFCK rising 2 EMAC25 Setup f...

Page 1122: ...ARM 27 Jul 11 SAM9X25 46 16 5 2 Timing extraction Figure 46 23 USART SPI Master Mode Figure 46 24 USART SPI Slave mode Mode 1 or 2 NSS SPI0 MSB LSB SPI1 CPOL 1 CPOL 0 MISO MOSI SCK SPI5 SPI2 SPI3 SPI4...

Page 1123: ...3 3v domain 2 1 5 MCK 0 9 1 5 MCK 1 1 ns SPI3 Chip Select Active to Serial Clock 1 8v domain 1 3 3v domain 2 1 5 SCK 2 0 1 5 SCK 2 6 ns SPI4 Output Data Setup Time 1 8v domain 1 3 3v domain 2 0 0 7 6...

Page 1124: ...PI11 MOSI Hold time after SCK falls 1 8v domain 1 3 3v domain 2 2 1 1 8 ns SPI12 NPCS0 setup to SCK rising 1 8v domain 1 3 3v domain 2 2 5 MCK 1 4 2 5 MCK 1 2 ns SPI13 NPCS0 hold after SCK falling 1 8...

Page 1125: ...1125 11054A ATARM 27 Jul 11 SAM9X25 1125 11054A ATARM 27 Jul 11 SAM9X25 47 Mechanical Overview 47 1 217 ball BGA Package Figure 47 1 217 ball BGA Package Drawing...

Page 1126: ...re YY manufactory year WW manufactory week V revision XXXXXXXXX lot number Table 47 1 Device and 217 ball BGA Package Maximum Weight 450 mg Table 47 2 217 ball BGA Package Characteristics Moisture Sen...

Page 1127: ...AM9X25 1127 11054A ATARM 27 Jul 11 SAM9X25 48 SAM9X25 Ordering Information Table 48 1 SAM9X25 Ordering Information Ordering Code Package Package Type Temperature Operating Range AT91SAM9X25 CU BGA217...

Page 1128: ...1128 11054A ATARM 27 Jul 11 SAM9X25 1128 11054A ATARM 27 Jul 11 SAM9X25...

Page 1129: ...r cannot be used Interrupt Mask Register reading always returns 0 Problem Fix Workaround None 49 4 USB High Speed Host Port UHPHS 49 4 1 UHPHS Packet Loss Issue in the UTMI Transceivers High Speed USB...

Page 1130: ...1130 11054A ATARM 27 Jul 11 SAM9X25...

Page 1131: ...1131 11054A ATARM 27 Jul 11 SAM9X25 Revision History Doc Rev 11054A Comments Change Request Ref 1st issue...

Page 1132: ...1132 11054A ATARM 27 Jul 11 SAM9X25...

Page 1133: ...s 19 6 3 External Memories 19 7 System Controller 21 7 1 Chip Identification 23 7 2 Backup Section 23 8 Peripherals 24 8 1 Peripheral Mapping 24 8 2 Peripheral Identifiers 24 8 3 Peripheral Signal Mul...

Page 1134: ...dvanced Interrupt Controller AIC 73 13 1 Description 73 13 2 Embedded Characteristics 73 13 3 Block Diagram 74 13 4 Application Block Diagram 74 13 5 AIC Detailed Block Diagram 74 13 6 I O Line Descri...

Page 1135: ...al Description 148 17 5 Watchdog Timer WDT User Interface 150 18 Shutdown Controller SHDWC 155 18 1 Description 155 18 2 Embedded Characteristics 155 18 3 Block Diagram 155 18 4 I O Lines Description...

Page 1136: ...cks 183 22 7 LP DDR DDR2 Clock 183 22 8 Software Modem Clock 183 22 9 Peripheral Clock Controller 183 22 10 Programmable Clock Output Controller 184 22 11 Programming Sequence 184 22 12 Clock Switchin...

Page 1137: ...5 Application Example 314 27 Programmable Multibit ECC Error Location Controller PMERRLOC 331 27 1 Description 331 27 2 Embedded Characteristics 331 27 3 Block Diagram 331 27 4 Functional Description...

Page 1138: ...Embedded Characteristics 421 30 3 DDRSDRC Module Diagram 423 30 4 Initialization Sequence 424 30 5 Functional Description 429 30 6 Software Interface SDRAM Organization Address Mapping 447 30 7 DDR S...

Page 1139: ...gy 607 34 8 High Speed MultiMediaCard Operations 609 34 9 SD SDIO Card Operation 628 34 10 CE ATA Operation 629 34 11 HSMCI Boot Operation Mode 631 34 12 HSMCI Transfer Done Timings 631 34 13 Write Pr...

Page 1140: ...scription 751 38 2 Embedded Characteristics 751 38 3 List of Abbreviations 752 38 4 Block Diagram 752 38 5 Application Block Diagram 753 38 6 Product Dependencies 753 38 7 Functional Description 754 3...

Page 1141: ...t Dependencies 907 41 7 CAN Controller Features 908 41 8 Functional Description 919 41 9 Controller Area Network CAN User Interface 932 42 Analog to digital Converter ADC 963 42 1 Description 963 42 2...

Page 1142: ...2 DC Characteristics 1091 46 3 Power Consumption 1093 46 4 Clock Characteristics 1095 46 5 Main Oscillator Characteristics 1095 46 6 12 MHz RC Oscillator Characteristics 1097 46 7 32 kHz Oscillator Ch...

Page 1143: ...xi 11054A ATARM 27 Jul 11 SAM9X25 49 2 Peripheral I O Controller PIO 1129 49 3 Real Time Clock RTC 1129 49 4 USB High Speed Host Port UHPHS 1129 Revision History 1131...

Page 1144: ...xii 11054A ATARM 27 Jul 11 SAM9X25...

Page 1145: ...RRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING...

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