Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
1119
11054A–ATARM–27-Jul-11
SAM9X25
46.16.4.2 Timing constraints
Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising
edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal stabilizes.
Figure 46-20 illustrates Min and Max accesses for EMAC3.
Figure 46-20. Min and Max access time of EMAC output signals
46.16.4.3 MII Mode
Notes: 1. VDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
2. See Note
(4)
of Table 46-38 .
Table 46-38. EMAC Signals Relative to EMDC
Symbol Parameter Min (ns) Max (ns)
EMAC
1
Setup for EMDIO from EMDC rising 10 ns
EMAC
2
Hold for EMDIO from EMDC rising 10 ns
EMAC
3
EMDIO toggling from EMDC rising 0 ns
(1)
300 ns
(1)
EMDC
EMDIO
EMAC
3 max
EMAC
1
EMAC
2
EMAC
4
EMAC
5
EMAC
3 min
Table 46-39. EMAC MII Timings
Symbol Parameter Min (ns) Max (ns)
EMAC
4
Setup for ECOL from ETXCK rising 10
EMAC
5
Hold for ECOL from ETXCK rising 10
EMAC
6
Setup for ECRS from ETXCK rising 10
EMAC
7
Hold for ECRS from ETXCK rising 10
EMAC
8
ETXER toggling from ETXCK rising 10
(2)
25
(2)
EMAC
9
ETXEN toggling from ETXCK rising 10
(2)
25
(2)
EMAC
10
ETX toggling from ETXCK rising 10
(2)
25
(2)
EMAC
11
Setup for ERX from ERXCK 10
EMAC
12
Hold for ERX from ERXCK 10
EMAC
13
Setup for ERXER from ERXCK 10
EMAC
14
Hold for ERXER from ERXCK 10
EMAC
15
Setup for ERXDV from ERXCK 10
EMAC
16
Hold for ERXDV from ERXCK 10