Atmel SAM9X25, Manual

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Figure 26-3. DDR2SDRC Multi-port Disabled (DDR_MP_EN = 0)
26.5.3.7 Programmable Multi-bit ECC Controller
For information on the PMECC Controller, refer to PMECC and PMERRLOC sections; also refer
to Boot Strategies Section, NAND Flash Boot: PMECC Error Detection and Correction.
26.5.3.8 NAND Flash Support
External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.
External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Inter-
face to the appropriate value enables the NAND Flash logic.
For details on this register, refer to
the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing
the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. See
Figure 26-4 on page
321 for more information. For details on these waveforms, refer to the Static Memory Controller
section.
NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21 of the EBI address bus. The command, address or data
words on the data bus of the NAND Flash device are distinguished by using their address within
the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B)
signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is
not selected, preventing the device from returning to standby mode.
Bus Matrix
DDR2SDRC
not used
not used
Port 0
EBI
(LP-)SDR
Device
NAND Flash
Device
not used