Atmel SAM9X25, Manual

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29.15 Programmable IO Delays
The external bus interface consists of a data bus, an address bus and control signals. The simul-
taneous switching outputs on these busses may lead to a peak of current in the internal and
external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be
adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8.
The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT). The
delay can differ between IOs supporting this feature. Delay can be modified per programming for
each IO. The minimal additional delay that can be programmed on a PAD suppporting this fea-
ture is 1/16 of the maximum programmable delay.
When programming 0x0 in fields “Delay1 to Delay 8”, no delay is added (reset value) and the
propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming
0xF in field “Delay1” the propagation delay of the corresponding pad is maximal.
SMC_DELAY1, SMC_DELAY2 allow to configure delay on D[15:0], SMC_DELAY1[3:0] corre-
sponds to D[0] and SMC_DELAY2[3:0] corresponds to D[8].
SMC_DELAY3, SMC_DELAY4 allow to configure delay on D[31:16], SMC_DELAY3[3:0] corre-
sponds to D[16] and SMC_DELAY4[3:0] corresponds to D[24]. In case of multiplexing through
the PIO controller, refer to the alternate function of D[31:16].
SMC_DELAY5, 6, 7 and 8 allow to configure delay on A[ 25 :0], SMC_DELAY5[3:0] corresponds
to A[0]. In case of multiplexing through the PIO controller, refer to the alternate function of
A[
25 :0].
Figure 29-36. Programmable IO Delays
DELAY1
D[0]
Programmable Delay Line
SMC
D_out[0]
D_in[0]
DELAY2
D[1]
Programmable Delay Line
D_out[1]
D_in[1]
DELAYx
D[n]
Programmable Delay Line
D_out[n]
D_in[n]
PIO
A[m]
Programmable Delay Line
PIO
DELAYy
A[m]