Atmel SAM9X25, Manual

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Figure 14-5. Wake-up Reset
14.4.5.3 User Reset
The User Reset is entered when a low level is detected on the NRST pin. When a falling edge
occurs on NRST (reset activation), internal reset lines are immediately asserted.
The Processor Reset and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle
processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e N R S T M a n a g e r g u a r a n t e e s t h a t t h e N R S T l i n e i s a s s e r t e d f o r
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
S LCK
periph_nre s et
proc_nre s et
M a in Su pply
POR o u tp u t
NR S T
(nr s t_o u t)
EXTERNAL RE S ET LENGTH
= 4 cycle s (ER S TL = 1)
MCK
Proce ss or S t a rt u p
ba ck u p_nre s et
Any
Fre q .
Re s ynch.
2 cycle s
R S TTYP
XXX 0x1 = W a keUp Re s et XXX