Atmel SAM9X25, Manual

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timings are identical. The pulse length of the first access to the page is defined with the
NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses
within the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in Table 29-7 :
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE
timings as page access timing (t
pa
) and the NRD_PULSE for accesses to the page (t
sa
), even if
the programmed value for t
pa
is shorter than the programmed value for t
sa
.
29.14.2 Byte Access Type in Page Mode
The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page
m o d e d e v i c e s t ha t r e q u i r e b y t e s e l e c t i o n s i g n a l s , c o n fi g u re t h e B A T f i e l d o f t h e
SMC_REGISTER to 0 (byte select access type).
29.14.3 Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
29.14.4 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 29-6 are identical, then the cur-
rent access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (t
sa
). Figure 29-35 illustrates access to an 8-bit memory device in
page mode, with 8-byte pages. Access to D1 causes a page access with a long access time
(t
pa
). Accesses to D3 and D7, though they are not sequential accesses, only require a short
access time (t
sa
).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
Table 29-7. Programming of Read Timings in Page Mode
Parameter Value Definition
READ_MODE ‘x’ No impact
NCS_RD_SETUP ‘x’ No impact
NCS_RD_PULSE t
pa
Access time of first access to the page
NRD_SETUP ‘x’ No impact
NRD_PULSE t
sa
Access time of subsequent accesses in the page
NRD_CYCLE ‘x’ No impact