Atmel SAM9X25, Manual

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202
11054A–ATARM–27-Jul-11
SAM9X25
202
11054A–ATARM–27-Jul-11
SAM9X25
22.13.11 PMC Master Clock Register
Name: PMC_MCKR
Address: 0xFFFFFC30
Access: Read-write
• CSS: Master/Processor Clock Source Selection
• PRES: Master/Processor Clock Prescaler
• MDIV: Master Clock Division
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – PLLADIV2 – – MDIV
7 6 5 4 3 2 1 0
– PRES – – CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLACK/PLLADIV2 is selected
3 UPLL_CLK UPLL Clock is selected
Value Name Description
0 CLOCK Selected clock
1 CLOCK_DIV2 Selected clock divided by 2
2 CLOCK_DIV4 Selected clock divided by 4
3 CLOCK_DIV8 Selected clock divided by 8
4 CLOCK_DIV16 Selected clock divided by 16
5 CLOCK_DIV32 Selected clock divided by 32
6 CLOCK_DIV64 Selected clock divided by 64
7 Reserved Reserved
Value Name Description
0 EQ_PCK
Master Clock is Prescaler Output Clock divided by 1.
Warning: SysClk DDR and DDRCK are not available.
1 PCK_DIV2
Master Clock is Prescaler Output Clock divided by 2.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
2 PCK_DIV4
Master Clock is Prescaler Output Clock divided by 4.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
3 PCK_DIV3
Master Clock is Prescaler Output Clock divided by 3.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.