Atmel SAM9X25, Manual

Page: 891 / 1145

891
11054A–ATARM–27-Jul-11
SAM9X25
891
11054A–ATARM–27-Jul-11
SAM9X25
Figure 40-5. Receiver Ready
40.5.2.4 Receiver Overrun
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA
Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the
OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control regis-
ter UART_CR with the bit RSTSTA (Reset Status) at 1.
Figure 40-6. Receiver Overrun
40.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in UART_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
Figure 40-7. Parity Error
40.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until
the control register UART_CR is written with the bit RSTSTA at 1.
D0 D1 D2 D3 D4 D5 D6 D7 P S
S D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 P S S D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTSTA
RXRDY
OVRE
stop
stop
stop
D0 D1 D2 D3 D4 D5 D6 D7 P S URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit