Atmel SAM9X25, Manual

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23. Parallel Input/Output Controller (PIO)
23.1 Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output
lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of
an embedded peripheral. This assures effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User
Interface.
Each I/O line of the PIO Controller features:
• An input change interrupt enabling level change detection on any I/O line.
• Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection
on any I/O line.
• A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.
• A debouncing filter providing rejection of unwanted pulses from key or push button
operations.
• Multi-drive capability similar to an open drain I/O line.
• Control of the pull-up and pull-down of the I/O line.
• Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a
single write operation.
23.2 Embedded Characteristics
• Up to 32 Programmable I/O Lines
• Fully Programmable through Set/Clear Registers
• Multiplexing of Four Peripheral Functions per I/O Line
• For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
– Input Change Interrupt
– Programmable Glitch Filter
– Programmable Debouncing Filter
– Multi-drive Option Enables Driving in Open Drain
– Programmable Pull Up on Each I/O Line
– Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
– Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge,
Low Level or High Level
– Lock of the Configuration by the Connected Peripheral
• Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
• Write Protect Registers
• Programmable Schmitt Trigger Inputs
• Programmable I/O Delay
• Programmable I/O Drive