Atmel SAM9X25, Manual

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SAM9X25
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SAM9X25
39.7.8.8 Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
Figure 39-41. Synch Field
The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section
39.7.1 ).
When the start bit of the Synch Field is detected, the counter is reset. Then during the next
8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) give the
new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) give the
new fractional part (LINFP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (US_BRGR).
If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE
in the Channel Status register (US_CSR) is set to 1. It is reset by writing bit RSTSTA to 1 in the
Control register (US_CR).
Figure 39-42. Slave Node Synchronization
The accuracy of the synchronization depends on several parameters:
• The nominal clock frequency (F
Nom
) (the theoretical slave node clock frequency)
Start
bit
Stop
bit
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit 2 Tbit
RXD
Clock
LINIDRX
Synchro Counter 000_0011_0001_0110_1101
US_BRGR
Clcok Divider (CD)
US_BRGR
Fractional Part (FP)
Initial CD
Initial FP
Reset
US_LINBRR
Clcok Divider (CD)
0000_0110_0010_1101
US_LINBRR
Fractional Part (FP)
101
Initial CD
Initial FP
Start
Bit
1 0 1 0 1 0 1 0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55