553
11054A–ATARM–27-Jul-11
SAM9X25
553
11054A–ATARM–27-Jul-11
SAM9X25
Figure 33-15.
Data OUT Transfer for an Endpoint with Two Banks
33.6.9.13
High Bandwidth Isochronous Endpoint OUT
Figure 33-16.
Bank Management, Example of Three Transactions per Microframe
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192
Mb/s (24 MB/s): 3x1024 data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data
packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at
least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
Token OUT
ACK
Data OUT 3
Token OUT
Data OUT 2
Token OUT
Data OUT 1
Data OUT 1
Data OUT 2
Data OUT 2
ACK
Cleared by Firmware
USB Bus
Packets
Virtual RX_BK_RDY
Bank 0
Virtual RX_BK_RDY
Bank 1
Set by Hardware
Data Payload written
in FIFO endpoint bank 1
FIFO (DPR)
Bank 0
Bank 1
Write by UDPHS Device
Write in progress
Read by Microcontroller
Read by Microcontroller
Set by Hardware,
Data payload written
in FIFO endpoint bank 0
Host sends first data payload
Microcontroller reads Data 1 in bank 0,
Host sends second data payload
Microcontroller reads Data 2 in bank 1,
Host sends third data payload
Cleared by Firmware
Write by Hardware
FIFO (DPR)
(UDPHS_EPTSTAx)
Interrupt pending
Interrupt pending
RX_BK_RDY = (virtual bank 0 | virtual bank 1)
Data OUT 1
Data OUT 3
MDATA0
MDATA0
MDATA1
DATA2
DATA2
MDATA1
t = 0
t = 52.5 μs
(40% of 125 μs)
RX_BK_RDY
t = 125 μs
RX_BK_RDY
USB line
Read Bank 3
Read Bank 2
Read Bank 1
Read Bank 1
USB bus
Transactions
Microcontroller FIFO
(DPR) Access
Summary of Contents for SAM9X25
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