Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
376
11054A–ATARM–27-Jul-11
SAM9X25
29.3 I/O Lines Description
29.4 Multiplexed Signals
Table 29-1. I/O Line Description
Name Description Type Active Level
NCS[7:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A1/NWR2/NBS2 Address Bit 1/Write 2/Byte 2 Select Signal Output Low
NWR3/NBS3 Write 3/Byte 3 Select Signal Output Low
A[25:2] Address Bus Output
D[31:0] Data Bus I/O
NWAIT External Wait Signal Input Low
Table 29-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
NWR0 NWE Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 378
A0 NBS0 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 378
NWR1 NBS1 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 378
A1 NWR2 NBS2
8-/16-bit or 32-bit data bus, see “Data Bus Width” on page 378 .
Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 378
NWR3 NBS3 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 378