Atmel SAM9X25, Manual

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SAM9X25
Note: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24
depending on memory power supplies. This switch is located in the EBICSA register in the Bus
Matrix user interface.
26.5.2 Product Dependencies
26.5.2.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
26.5.3 Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
• the Static Memory Controller (SMC)
• the DDR2/SDRAM Controller (DDR2SDRC)
• the Programmable Multi-bit ECC Controller (PMECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable NAND Flash support logic
26.5.3.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDR Control-
ler without delaying the other external Memory Controller accesses.
26.5.3.2 Pull-up and Pull-down Control
The EBI_CSA registers in the Chip Configuration User Interface enable on-chip pull-up and pull-
down resistors on data bus lines not multiplexed with the PIO Controller lines. The pull-down
resistors are enabled after reset. The bits, EBIx_DBPUC and EBI_DBPDC, control the pull-up
RAS VDDIOM RAS RAS –
CAS VDDIOM CAS CAS –
SDWE VDDIOM WE WE –
Pxx VDDNF – – CE
Pxx VDDNF – – RDY
Table 26-4. EBI Pins and External Device Connections
Signals:
EBI_
Power supply Pins of the Interfaced Device
DDR2/LPDDR SDR/LPSDR NAND Flash
Controller DDRC SDRAMC NFC