Atmel SAM9X25, Manual

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Figure 42-2. Sequence of ADC conversions
42.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.
Analog inputs between these voltages convert to values based on a linear conversion.
42.6.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the
LOWRES bit in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is
the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the
ADC switches to the lowest resolution and the conversion results can be read in the lowest sig-
nificant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
42.6.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the chan-
nel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected DMA channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR
clears the DRDY bit and EOC bit corresponding to the last converted channel.
ADCClock
LCDR
ADC_ON
ADC_ S EL
DRDY
ADC_ S t a rt
CH0 CH1
CH0
CH2
CH1
S t a rt Up Time
( a nd tr a cking of CH0)
Conver s ion of CH0 Conver s ion of CH1 Tr a cking of CH1
Tr a cking of CH2
ADC_eoc
Trigger event
(H a rd or S oft)
An
a
log cell IO
s