Atmel SAM9X25, Manual

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11054A–ATARM–27-Jul-11
SAM9X25
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11054A–ATARM–27-Jul-11
SAM9X25
• Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
• Write CKGR_PLLCOUNT field in PMC_UCKR register.
• Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
• Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
• Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
• Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB register.
• Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register.
USBDIV must be 9 (division by 10) if UPLLCK is selected.
• Enable OHCI clocks, UHP bit in PMC_SCER register.
For OHCI Full-speed operations only, the user has to perform the following:
• Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER register.
• Select PLLACK as Input clock of OHCI part, USBS bit in PMC_USB register.
• Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register.
USBDIV value is to calculated regarding the PLLACK value and USB Full-speed accuracy.
• Enable the OHCI clocks, UHP bit in PMC_SCER register.
Figure 32-3. UHP Clock Trees
UTMI tr a n s ceiver
EHCI
U s er
Interf a ce
AHB
UHP4
8
M
OHCI
U s er
Interf a ce
U S B 2.0 EHCI
Ho s t Controller
U S B 1.1 OHCI
Ho s t Controller
Root H ub
a nd
Ho s t S IE
Port
Ro u ter
UPLL (4 8 0 MHz)
3 0 MHz
3 0 MHz
UHP12M
OHCI
M as ter
Interf a ce
EHCI
M as ter
Interf a ce
MCK
OHCI clock s
UTMI tr a n s ceiver
F S tr a n s ceiver