Atmel SAM9X25, Manual

Page: 452 / 1145

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11054A–ATARM–27-Jul-11
SAM9X25
452
11054A–ATARM–27-Jul-11
SAM9X25
30.7.1 DDRSDRC Mode Register
Name: DDRSDRC_MR
Address: 0xFFFFE800
Access: Read-write
Reset: See Table 30-16
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 466 .
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini-
tialize the SDRAM device and to activate deep power-down mode.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – MODE
MODE Description
000
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed
by a write to the SDRAM.
001
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this
mode, command must be followed by a write to the SDRAM.
010
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
011
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
100
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a
write to the SDRAM.
101
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of
the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM.
The write in the SDRAM must be done in the appropriate bank.
110 Deep power mode: Access to deep power-down mode
111 Reserved