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Remote Control
R&S
®
ZNB/ZNBT
767
User Manual 1173.9163.02 ─ 55
Bit No.
Meaning
6
MSS bit
(master status summary bit)
This bit is set if the instrument triggers a service request. This is the case if one of the
other bits of this register is set together with its mask bit in the service request enable reg-
ister SRE.
7
OPERation status register summary bit
This bit is set if an EVENt bit is set in the OPERation-Status register and the associated
ENABle bit is set to 1.
The bit indicates that the instrument is currently performing an action. The type of action
can be determined by polling the
Related common commands
The STB is read out using the command
*STB?
or a
.
The SRE can be set using command
*SRE
and read using
*SRE?
.
7.5.3.2
IST Flag and PPE
(SRQ), the IST flag combines the entire status infor-
mation in a single bit. It can be queried by means of a
The Parallel Poll Enable (PPE) register determines which bits of the STB contribute to
the IST flag. The bits of the STB are ANDed with the corresponding bits of the PPE,
with bit 6 being used as well in contrast to the SRE. The IST flag results from the
ORing of all results.
Related common commands
The IST flag is queried using the common command
*IST?
. The PPE can be set
using
*PRE
and read using
*PRE?
.
See also
.
7.5.3.3
ESR and ESE
The Event Status Register (ESR) indicates general instrument states. It is linked to the
Event Status Enable (ESE) register on a bit-by-bit basis.
●
The ESR corresponds to the CONDition part of an SCPI register indicating the cur-
rent instrument state (although reading is destructive).
●
The ESE corresponds to the ENABle part of an SCPI register. If a bit is set in the
ESE and the associated bit in the ESR changes from 0 to 1, the ESB bit in the STa-
tus Byte is set.
The bits in the ESR are defined as follows:
Status Reporting System