GD32A50x User Manual
348
Channel output prepare signal
As is shown in
Figure 18-14. Channel output compare principle
Figure 18-16. Channel output compare principle (with complementary
output when MCHxMSEL = 2’11, x=0,1,2,3)
, when TIMERx is configured in compare match
output mode, a middle signal named OxCPRE or MOxCPRE (channel x output or
multi mode
channel x output prepare signal) will be generated before the channel outputs signal.
The OxCPRE and MOxCPRE signal have several types of output function. The OxCPRE
signal type is defined by configuring the CHxCOMCTL bit and the MOxCPRE signal type is
defined by configuring the MCHxCOMCTL bit.
Take OxCPRE as an example for description below, these include keeping the original level
by configuring the CHxCOMCTL field to 0x00, setting to high by configuring the CHxCOMCTL
field to 0x01, setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal
by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of
the TIMERx_CHxCV register.
The PWM mode 0/ PWM mode 1 output is another output type of OxCPRE which is setup by
configuring the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is
changed according to the counting direction and the relationship between the counter value
and the TIMERx_CHxCV content. Refer to the definition of relative bit for more details.
Another special function of the OxCPRE signal is forced output which can be achieved by
configuring the CHxCOMCTL field to 0x04/ 0x05. The output can be forced to an
inactive/active level irrespective of the comparison condition between the values of the
counter and the TIMERx_CHxCV.
Configure the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register, the OxCPRE signal
can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high
level. The OxCPRE signal will not return to its active level until the next update event occurs.
Channel output complementary PWM
The outputs of CHx_O and MCHx_O have three situations:
MCHxMSEL=2’b00: The MCHx_O output is independent from the CHx_O output;
MCHxMSEL=2’b01: The MCHx_O output is the same as the CHx_O output and the
MCHxOMCTL bits are not used in the generation of the MCHx_O output;
MCHxMSEL=2’b11: The outputs of MCHx_O and CHx_O are complementary and the
MCHxOMCTL bits are not used in the generation of the MCHx_O output.
Function of complementary is for a pair of channels, CHx_O and MCHx_O, the two output
signals cannot be active at the same time. The TIMERx has 4 pairs of channels, all the four
pairs have this function. The complementary signals CHx_O and MCHx_O are controlled by
a group of parameters: the CHxEN and MCHxEN bits in the TIMERx_CHCTL2 register, the
POEN, ROS and IOS bits in the TIMERx_CCHP register(when CHx_O and MCHx_O
channels has separated deadtime value and break function, please refer to