GD32A50x User Manual
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with input data on pin1.
5.
Set the value of register MFCOM_TMCMPx as 0x00003F01, configure 32-bit transfer
with baud rate of divide by 4 of the MFCOM clock. Set TMCVALUE [15:8] = (number of
bits x 2) - 1. Set TMCVALUE [7:0] = (baud rate divider / 2) - 1.
6.
Set the bits TMOUT[1:0], TMDIS[2:0], TMEN[2:0] TMSTOP[1:0], and TMSTART as 0b01,
0b010, 0b010, 0b10, and 0b1 in register MFCOM_TMCFGx respectively,
configure start
bit, stop bit, enable on trigger high and disable on compare, initial clock state is logic 0.
7.
Set the bits TRIGSEL[3:0], TRIGPL, TRIGSRC, TMPCFG[1:0], TMPSEL[2:0], and
TMMOD[1:0] as 0b0001, 0b1, 0b1, 0b11, 0b010, and 0b01 in register MFCOM_TMCTLx
respectively, configure dual 8-bit counter using pin 2 output (shift clock), with shifter 0
flag as the inverted trigger. Set PINPL to invert the output shift clock. Set the value of
register MFCOM_TCMP(x+1) as 0x0000FFFF, and never compare.
8.
Set the value of register MFCOM_TMCMP(x+1) as 0x0000FFFF, never compare.
9.
Set the bits TMDIS[2:0] and TMEN[2:0] as 0b001 and 0b001 in register
MFCOM_TMCFG(x+1) respectively, enable when timer 0 is enabled and disable when
timer 0 is disabled.
10.
Set the bits TMPCFG[1:0], TMPSEL[2:0], TMPPL and TMMOD[1:0] as 0b11, 0b011, 0b1,
and 0b11 in register MFCOM_TMCTL(x+1) respectively, configure 16-bit counter and
output on pin 1. Trigger is internal using shifter 0 flag.
11.
Set the bit SBUF[31:0] as data to transmit in register MFCOM_SBUFx, transmit data can
be written to MFCOM_SBUFx, use the shifter status flag to indicate when data can be
written using interrupt or DMA request. Can support MSB first transfer by writing to
MFCOM_SBUFBBSx register instead.
12.
Set the bit SBUF[31:0] as data to receive in register MFCOM_SBUF(x+1), received data
can be read from MFCOM_SBUFBYSx, use the sifter status fag to indicate when data
can be read using interrupt or DMA request. Can support MSB first transfer by reading
from MFCOM_SBUFBISx register instead.
SPI master (CPHA=1) configuration
1.
Set the bits SSTOP[1:0] and SSTART[1:0] as 0b10 and 0b01 in register MFCOM_SCFGx
respectively, start bit loads data on first shift.
2.
Set the bits SPCFG[1:0] and SMOD[1:0] as 0b11 and 0b010 in register MFCOM_SCTLx
respectively, configure transmit using timer 0 on negedge of clock with output data on
pin0.
3.
Keep the value of register MFCOM_SCFG(x+1) as default, start and stop bit disabled.
4.
Set the bits TMPL, SPSEL[2:0], and SMOD[1:0] as 0b1, 0b001, and 0b001 in register
MFCOM_SCTL(x+1) respectively, configure receive using timer 0 on negedge of clock
with input data on pin1.
5.
Set the value of register MFCOM_TCMPx as 0x00003F01, configure 32-bit transfer with
baud rate of divide by 4 of the MFCOM clock. Set TMCVALUE [15:8] = (number of bits x
2) - 1. Set TMCVALUE [7:0] = (baud rate divider / 2) - 1.
6.
Set the bits TMOUT[1:0], TMDIS[2:0], TMEN[2:0] TMSTOP[1:0], and TMSTART as 0b01,
0b010, 0b010, 0b10, and 0b1 in register MFCOM_TMCFGx respectively,
configure start
bit, stop bit, enable on trigger high and disable on compare, initial clock state is logic 0.
