Stanford Research Systems RGA100, Operating Manual And Programming Reference

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10-10 Description of Schematics
SRS Residual Gas Analyzer
summed. The charge pump works as follows: as the potential on the rod reaches a peak,
the 0.5 pF capacitor (C750 on the PCB which holds the flange socket) is charged to the
maximum voltage, Vp + Vdc - Vdiode with current flowing to ground via D303, a
Schottky diode. During the next half cycle, C750 is charged to -Vp + VDC + Vdiode
with current flowing through D302 from the virtual ground at the inverting input of
U305. The total charge transfer to the op-amp is C x dV = C x (Vpp-2Vdiode). This
charge is pumped every cycle from two charge pumps, so the current is I = 2fC(Vpp-
2Vdiode). For C=0.5pF and f=2.7648 MHz, and ignoring Vdiode, the current is
2.76
P
A/Vpp. This current flows through the 698
:
feedback resistor, R312 in parallel
with R322, which is selected to calibrate the detector’’s sensitivity.
The output of the charge pump’’s I/V converter (U305) is filtered and attenuated by the
3rd order elliptic filter (C303-305 and L300) which has a characteristic impedance of
200
:
and a notch at 5.6MHz, which corresponds to the second harmonic of the detected
RF signal. The potentiometer at the output of the filter (P300) is adjusted to provide a
voltage of Vpp/1000. This signal is used as the feedback signal to control the RF
amplitude.
The adjustment of P300, the RF amplitude detection gain potentiometer, is very
important in order to maintain constant resolution and sensitivity throughout a scan. P300
should be adjusted so that He and Kr have the same resolution with RES_CTL at a fixed
nominal level of +2.50VDC. From here, empirical adjustments to RES_CTL vs. amu may
be made to optimize the instrument's performance, but to first order, RES_CTL will be a
constant. (Factory cal only with DS=0.)
RF Amplitude Control
The detected RF amplitude signal, VPP/1000, is compared to the RF level control
(RF_SET) from the 18-bit DAC U303. If the detected level is below the set level then the
output of U306 slews upward, increasing the primary drive, increasing the RF level, until
the RF level reaches the set level. U306 is configured as a differential amplifier with a
gain of 5, which uses the ground reference from the bottom PCB, so as to reduce the
effects of noise and ground offsets between the PCBs. The CPU may scan the mass filter
by ramping the 18-bit DAC output between 8.56mV (for 1 amu) and 2.56V (for 300
amu).
Foldback Current Limiting
The RF output is approximately linear in the RF primary drive current. The scale factors
for the detected RF_SET and the measured RF primary drive current (RF_PRI = 1.5V/A)
were chosen so that RF_SET should always be larger than RF_PRI if the system is
operating properly. In the case of a failure which causes excessive primary drive current,
the output of the difference amplifier, U304B, goes positive as RF_PRI goes above
RF_SET. The output of U304 will limit the primary drive current as the current through
D304 increases. In this case, which is detected by the CPU as RF_PRI>RF_SET, the RF
level will be less than the level set by the 18-bit DAC.
The 18-bit DAC output is also used to set the DC potentials applied to the mass filter.
RF_SET is multiplied by 4 by the differential amplifier U304A, which uses the bottom
PCB for its ground reference. The output of U304A is passed to the bottom PCB via
JP301 to control the DC bias sources.