Stanford Research Systems RGA100, Operating Manual And Programming Reference

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Description of Schematics 10-9
SRS Residual Gas Analyzer
The CPU can measure the offset of the input multiplexer, op-amp, and A/D converter by
selecting input X7 (the circuit ground). The measured offset is subtracted from readings
taken for the other inputs.
A conversion is initiated by -CS_ADC16 going low while R/-C is low. -CS_ADC16 is
asserted when the 675 Hz convert clock from the 74HC4020 (U108) goes low provided
that CS_VETO (MISC port bit 7) is low. The 675 Hz convert clock going low also
initiates an -IRQ to the CPU. In response to the -IRQ, the CPU sets CS_VETO high
(which sets -CS_ADC16 high) and sets R/-C high to allow the data to be read. The -
BUSY output will remain low for up to 20
P
s during a conversion. When -BUSY goes
high, the CPU returns CS_VETO low, which again asserts the -CS_ADC16 (this time
with R/-C high), and reads the data from the ADC via the SPI. Since the ADC shifts its
data on the rising edge of the data clock (i.e. data should be read on the falling edge of
the data clock) the inverted SPI clock is used as the data clock to the ADC. This will also
permit simultaneous transmission of data to the 18-bit RF amplitude control D/A. The
CPU sets R/-C low after the data is read to prepare the A/D for the next conversion cycle.
Power-up Conditioning
The A/D reference output (+2.50VDC) is amplified, buffered, and inverted by U302A&B
to provide system references of +/-5.00VDC. These references are set to zero volts when
the system is reset so that other analog signals (such as the HV and filament control
signals) will stay at zero until set by the microcontroller.
The triple 2:1 analog switch U301, a 74HC4053, is used to make certain that various
circuits remain off when the system is reset, until the CPU can establish the system
environment. Upon reset the dual flip-flop U300 is reset. The output of the second flip-
flop, which controls all three channels of the analog switch, will return high with the
second port strobe from the CPU to the MISC bits port. Immediately following a reset,
EMIT_CTL will be low (to multiplex EMIT_SET to control the duty cycle of the
filament heater circuit directly), the
r
5.00REFs will be set to zero (so that all the analog
control signals will be zero), and the output current from the 18-bit DAC which controls
the RF amplitude will be shunted to ground.
Schematic name: QMSE_T3)
DC Control Voltages
U307, a MAX528 octal 8-bit DAC, provides DC voltages to control various parameters
in the system. Each output has a range from 0 to 4.98V with a step size of about 19.5
mV. The eight outputs and their functions are listed here:
0 RES_CTL This output (-2.5V and times 1) increases the rods' DC.
1 EMIT_SET This output (times 1 or 10mA/V) sets the emission current.
4 RPL_SET This output (times -20) sets the repeller and filament bias.
3 FOC_SET This output (times -30) sets the focus plate bias.
7 HV_SET This output (times -500) sets the electron multiplier bias.
5 +OFFSET This output (-2.5 & times .001) fixes the detector offset.
5 -OFFSET This output (-2.5 & times .001) fixes the reference offset.
6 CAL This output (-2.5V then times -2) is the calibration source.
RF Amplitude Detection
The amplitude of the RF is detected by a full-wave charge pump detector. In order to
provide a symmetrical load to the generator, the amplitude on both rods is detected and