Stanford Research Systems RGA100, Operating Manual And Programming Reference

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10-8 Description of Schematics
SRS Residual Gas Analyzer
Since the A/D convert rate is a sub-multiple of all the other system clocks, crosstalk from
the clocks will be synchronous, and will generate a fixed offset to the signal (which may
be measured and subtracted) instead of noise.
The clock division for the 28.8 kBaud rate is done by the microcontroller; the rest of the
clock division is done by U108, a 74HC4020 14-stage ripple divider. The 172.8 kHz
square wave is formed into a 100 ns wide pulse to be used as a switching power supply
sync pulse, which is divided by two by the power supply controller. U109, a 74HC74
dual D-type flip-flop, provides the complimentary drive required for the RF and high-
voltage inverter circuits. Either of these drives may be turned off (both Q and -Q outputs
set high) by setting the control bits RF_ON or HV_ON low.
RS232 Interface
The microcontroller communicates with a host computer via the RS232 interface. The
RS232 interface is configured as a DCE (data communications equipment) at a fixed
baud rate of 28.8k, with hardware handshaking via CTS (clear-to-send) and RTS
(request-to-send), and uses a PC compatible female DB9 connector. So, the quadrupole
will transmit data on pin 2, receive data on pin 3, assert CTS on pin 8, and look for RTS
on pin 7. Pin 5 is the signal and chassis ground.
Schematic name: QMSE_T2
I/V calibration
The current signal from the Faraday cup or electron multiplier is converted to a voltage
by the logarithmic I/V converter (see schematic QMSE_V1). This converter requires
careful calibration and bias in order to assure accurate readings over its 8 decade range. A
programmable voltage source (U209 and associated components) can provide voltages
from microvolts to volts, which are applied to the I/V converter via a 1G
:
resistor to
generate calibration currents from femtoamps to nanoamps. The calibration source is also
used to bias the I/V converter during scans to establish the bandwidth/noise floor
tradeoff.
A second I/V converter channel is biased by the calibration source to allow for
temperature compensation of the detection channel. Both I/V converters are biased by
equal currents from the calibration source, so that their output voltages are nearly the
same when there is no ion current being detected. The outputs of each I/V converter may
be read via the 16-bit A/D for calibration and offset nulling. The outputs of the I/V
converters are subtracted in a differential amplifier (U211A) with a gain of 5.23 and a
bandwidth of 1 kHz.
The differential amplifier is followed by a Butterworth filter (U211B) with a gain of 1.59,
a -3 dB point of 300 Hz, and a roll-off of -12 dB/octave. The filter is used to reduce the
noise on the signal which is above the Nyquist bandwidth for a 675 Hz sampling rate. (In
low bias current cases, the bandwidth of the signal is much lower, per the diode time
constant.) R233 insures that the output of the filter cannot exceed the +/-5V range of the
1:8 multiplexer at the input to the 16-bit A/D converter.
A/D Conversion
Several different signals and a ground reference may be multiplexed to a 16-bit A/D
converter by U201, a 74HC4051. The control bits MPX_0-2 are used to select one of the
8 inputs. The selected input is amplified by U202A by 2x to scale the input for the +/-
10V range of the A/D converter, U203.